1nm Chips on the Horizon: Rapidus Aims to Produce 1 nm Node by 2027

Rapidus sets its sights on achievable goals for the 1nm-class manufacturing processes, targeting a 10% to 20% improvement in power efficiency and performance compared to its own 2nm fabrication technology.

Introduction:

In a significant move toward advancing semiconductor technology, Rapidus, a Japanese government-funded startup chipmaker, has joined forces with the University of Tokyo and France’s Leti research institute to produce 1 nm technology.

This collaboration aims to pioneer the development of groundbreaking 1- 1.4nm process technologies, with an expected production launch in 2027.

The partnership signals a strategic initiative to enhance Japan’s position in the global semiconductor industry. This brings together leading experts and organizations for a decade-long journey of sustainable technology collaboration.

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The Collaborative Landscape by Rapidus to produce 1 nm:

The collaboration involves not only Rapidus and Leti but also includes the Leading-Edge Semiconductor Technology Center (LSTC), the University of Tokyo, Riken Research Institute, and other national universities.

This comprehensive approach establishes a memorandum of understanding signed in October, with a vision to define and pursue long-term research and development roadmaps over the next decade.

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Key Objectives of the Collaboration:

The undisclosed terms of the collaboration outline the respective roles of the participating entities. Leti, renowned for its research prowess, will focus on exploring novel transistor structures.

Rapidus and other Japanese partners will contribute through staff exchanges, fundamental research sharing, and the assessment and testing of prototypes.

Rapidus sets its sights on achievable goals for the 1nm-class manufacturing processes, targeting a 10% to 20% improvement in power efficiency and performance compared to its own 2nm fabrication technology.

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Technological Milestones and Industry Adoption for Rapidus 1 nm :

Mainstream adoption of 1nm process technology is expected to occur in the 2030s, following the adoption of 2nm, 1.8nm, and 1.4nm nodes throughout this decade.

As the semiconductor landscape evolves, the necessity for new transistor structures becomes evident. Industry experts anticipate that vertically-stacked complementary field effect transistors (CFETs) may replace gate-all-around FET. This signals a potential paradigm shift in chip manufacturing.

Building Global Partnerships:

Rapidus has previously engaged with IBM and Belgium’s Imec for the design of a 2nm f process.

The collaborative efforts aim to initiate pilot 2nm chip production in 2025, with high-volume production set for 2027.

The collaboration with Leti does not exclude further partnerships with IBM and Imec; instead, it creates a synergistic environment where each organization complements the strengths of the others.

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Japan’s Semiconductor Industry through Rapidus 1 nm :

Collaboration with Leti, IBM, and Imec, represents a vital step in revitalizing Japan’s position in the semiconductor industry.

By fostering international partnerships and leveraging the expertise of leading research institutions, Japan aims to stay at the forefront of semiconductor innovation. This also ensures continued competitiveness on the global stage.

Conclusion:

Rapidus, in collaboration with the University of Tokyo and Leti, will pioneer 1nm chip technology.

This strategic collaboration, with its emphasis on sustainable long-term goals and global partnerships, signifies a pivotal moment in the evolution of semiconductor technology.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Priyadarshi is a prominent figure in the world of technology and semiconductors. With a deep passion for innovation and a keen understanding of the intricacies of the semiconductor industry, Kumar has established himself as a thought leader and expert in the field. He is the founder of Techovedas, India’s first semiconductor and AI tech media company, where he shares insights, analysis, and trends related to the semiconductor and AI industries.

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. He couldn’t find joy working in the fab and moved to India. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL)

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