40,000x Data Retention Boost: NEO Reveals World’s First 3D NAND-Like DRAM

NEO Semiconductor introduces a groundbreaking Floating Body Cell Mechanism for 3D X-DRAM at the IEEE International Memory Workshop 2024

Introduction

In a significant breakthrough for the memory industry, NEO Semiconductor has revealed an innovative Floating Body Cell Mechanism designed to enhance the performance of 3D X-DRAM. Presented by Andy Hsu, Founder & CEO of NEO Semiconductor, at the IEEE International Memory Workshop (IMW) 2024 in Seoul, Republic of Korea, this new mechanism promises to revolutionize data retention and sensing capabilities in DRAM technology.

The traditional 2D Floating Body Cell uses body effect resulting in small sensing window. NEO’s 3D X-DRAM Floating Body Cell BCM mechanism uses back-gate voltage to change channel depth, which increases data retention by 40,000X and sensing window by 20X.

3D X-DRAM: This is a new type of DRAM architecture developed by NEO Semiconductor. It’s based on a 3D NAND-like structure, which could potentially offer significant advantages over traditional 2D DRAM.

Floating Body Cell Mechanism: This is the innovation that NEO Semiconductor revealed at IMW. It significantly improves the performance of 3D X-DRAM. They claim it can increase data retention by 40,000 times and sensing window by 20 times .

Benefits: With this new mechanism, 3D X-DRAM promises to be much denser (offering up to 8 times the density of today’s DRAM), consume less power, and have a smaller footprint than current DRAM technology.

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The Groundbreaking Technology: 3D NAND-Like DRAM

Traditional vs. Innovative Approaches

Traditional 2D Floating Body Cells (FBCs) in semiconductor memory devices use the body effect to alter the cell current. The body effect refers to the influence of the voltage applied to the body (or substrate) of a transistor on its threshold voltage. In FBCs, this effect is utilized to modulate the current flowing through the cell, which in turn is used to sense and store data. However, this method results in a limited sensing window.

The sensing window is the range of current or voltage that can be distinctly differentiated between different states (e.g., ‘0’ and ‘1’). A limited sensing window restricts the reliability and performance of the memory device, as it becomes harder to distinguish between different stored states.

NEO Semiconductor’s new approach, termed Back-gate Channel-depth Modulation (BCM), introduces a novel method for controlling the channel properties of the transistor used in memory cells. Instead of relying on the body effect, BCM leverages a back-gate voltage to adjust the depth of the channel, which is the region in the transistor where current flows between the source and drain terminals.

Back-gate Voltage Control:

In BCM, a voltage is applied to a back-gate terminal that is located beneath the channel of the transistor. This back-gate voltage can modulate the depth and properties of the channel more effectively than the traditional body effect.

Channel Depth Adjustment:

The channel depth, which is the distance between the channel and the back-gate, is crucial in determining the current flow characteristics. By finely controlling this depth with the back-gate voltage, BCM allows for more precise modulation of the channel properties.

Expanded Sensing Window:

With better control over the channel depth, BCM significantly expands the sensing window. This expanded sensing window means there is a greater range of current or voltage levels that can be distinctly sensed, leading to more reliable data readouts.

Improved Data Retention:

Data retention refers to the ability of the memory cell to retain the stored information over time. BCM enhances data retention by providing more stable control over the channel properties, reducing leakage and other factors that can degrade stored data.

Enhanced Performance:

The ability to modulate the channel depth more effectively allows for higher performance in terms of speed and power consumption. Memory cells utilizing BCM can operate faster and with greater efficiency, as the back-gate control provides a more direct and responsive means of adjusting cell behavior.

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Technical Insights: 3D NAND-Like DRAM

NEO Semiconductor builds its 3D X-DRAM on a novel 3D NAND-like DRAM cell array structure using floating body cell technology. Manufacturers can produce this structure using existing 3D NAND processes, which are already mature and widely used in the industry.

3D X-DRAM Density: The technology is capable of achieving a density of 128 Gb with 300 layers, which is eight times the density of current DRAM.

Power Efficiency: By reducing the chip’s footprint and power consumption, NEO’s 3D X-DRAM not only enhances performance but also improves energy efficiency.

Data Retention Increase: The BCM mechanism enhances data retention by an astonishing 40,000 times compared to traditional methods.

Sensing Window Expansion: The sensing window is amplified by 20 times, enabling faster and more reliable DRAM performance.

Impact on the Industry: 3D NAND-Like DRAM

Addressing Capacity Scaling Bottlenecks

NEO’s BCM mechanism for 3D X-DRAM addresses one of the significant challenges in the DRAM industry: the capacity scaling bottleneck. As DRAM technology continues to evolve, the ability to scale efficiently and effectively becomes paramount.

  • Reduced Refresh Frequency: The improved data retention significantly reduces the need for frequent refresh cycles, thereby saving power.
  • Enhanced Reliability: With a larger sensing window, DRAM can achieve faster read and write speeds, contributing to overall system reliability and performance.

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Future Prospects: 3D NAND-Like DRAM

NEO Semiconductor’s advancements are set to propel the DRAM industry into a new era of 3D architectures, substantially improving upon existing 2D DRAM technologies.

3D Era Leadership: NEO’s innovations position it at the forefront of the transition to 3D DRAM, paving the way for future developments in the memory industry.

Broad Applications: The enhanced performance and reduced power consumption make 3D X-DRAM ideal for a wide range of applications, including 5G, AI, and other high-speed, high-density computing environments.

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What’s the big deal of 3D NAND-Like DRAM

More Memory in Less Space: Current DRAM is reaching its limits in terms of how much data it can store in a fixed area. 3D X-DRAM, with its potential for 8 times the density, could pack significantly more memory into a chip. This translates to devices with larger storage capacities or sleeker designs with smaller memory footprints.

Faster and More Efficient Memory: The floating body cell mechanism promises a 40,000x boost in data retention and a 20x wider sensing window. This means the memory can hold onto data for much longer and differentiate between stored values more easily. This could lead to faster data access times and potentially lower power consumption due to less frequent refreshes.

In simpler terms, 3D X-DRAM has the potential to be a significant leap forward in memory technology. This offers both more storage and faster performance while potentially being more compact and more power-efficient. This could benefit a wide range of devices, from smartphones and laptops to high-performance computers and data servers.

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Conclusion

NEO Semiconductor’s presentation at IEEE IMW 2024 has highlighted a pivotal moment in the evolution of DRAM technology. With the BCM mechanism for 3D X-DRAM, NEO Semiconductor is pushing the limits of memory technology. This innovation sets the stage for future breakthroughs. NEO’s advancements promise faster, more reliable, and energy-efficient memory solutions. These improvements will drive progress across many technological fields.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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