You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's/Sub-systems/SOC's.
In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver afully verified, synthesis/timing clean design.
Innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
If you are a DFT engineer with expertise in GPU technologies and Engineering (architecture, IP, SoC, software) and are passionate about defining the future of graphics computing and AI, we have opportunities for you.
We are searching for an IC Layout Manager in our DRAM Engineering Group in India.
Our team is responsible for carrying out Performance Analysis on CPUs and System IP put together as SoCs in pre- and post-Silicon environments.
We will use our design abilities, coding expertise, and creativity to help deliver innovative real-time firmware and kernel mode drivers for a low power, high performance computer vision accelerator engine.