Chip Stacking Gets a Boost: Siemens and Samsung Foundry Team Up for Powerful 3D-IC Solutions

They're developing new techniques for making 3D-ICs at advanced manufacturing nodes. 3D-ICs stack multiple layers of chips on top of each other, offering benefits like increased performance and miniaturization.

Introduction

Siemens Digital Industries Software announced a strategic collaboration with Samsung Foundry to enhance the development and manufacturing of multi-die packaged designs at advanced nodes. This partnership has resulted in new capabilities and product certifications for Siemens’ industry-leading IC design and verification technologies.

3D-IC Development: They’re developing new techniques for making 3D-ICs at advanced manufacturing nodes. 3D-ICs stack multiple layers of chips on top of each other, offering benefits like increased performance and miniaturization.

EDA Tool Certification: Siemens is certifying its Electronic Design Automation (EDA) software for Samsung’s latest chip manufacturing processes. EDA tools help design and verify integrated circuits. This certification ensures compatibility and smoother chip design for mutual customers.

Focus on Advanced Packaging: Siemens’ Xpedition software suite is being updated to seamlessly integrate with Samsung’s packaging processes. This allows for better design and analysis of 3D and 2.5D chip packages.

Parasitic Extraction Tools: Siemens’ Calibre tools are being certified for Samsung’s advanced processes. These tools extract parasitic capacitance and resistance, which are crucial for accurate chip design and performance analysis.

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About Siemens Digital Industries Software

Siemens Digital Industries Software assists organizations of all sizes in digital transformation.

They use software, hardware, and services from the Siemens Xcelerator business platform. Siemens’ software, along with the comprehensive digital twin, helps companies optimize design, engineering, and manufacturing processes.

This enables the transformation of today’s ideas into sustainable products for the future.

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Advancing 3D-IC Manufacturability

Siemens and Samsung Foundry have updated process design kits (PDKs) to integrate seamlessly with Siemens’ Xpedition™ Substrate Integrator (XSI) and Xpedition™ Package Designer (XPD) software.

This integration allows Samsung to provide robust PDK updates to customers with minimal disruption, empowering engineers to create comprehensive digital twin models of multi-die devices.

These models facilitate seamless design integrations, driving all downstream design, analysis, verification, and signoff activities.

Samsung also evaluated Siemens’ High Density Advanced Packaging (HDAP) flow for their multi-die-integration (MDI) packaging process.

Siemens’ Calibre® xACT™ 3D and Calibre xL parasitic extraction tools, part of the Calibre® nmPlatform, were certified for Samsung’s advanced nodes.

These tools enable quick and accurate extraction of register clock parasitics in complex 2.5D and 3D packaging configurations, supporting signal integrity-aware analysis of high bandwidth memory (HBM) channels on 3.5D silicon interposers.

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Comprehensive Certification of Siemens EDA Products

Samsung has certified multiple Siemens EDA product lines and reference flows, including:

  • Calibre nmPlatform: This platform, including the new Calibre® DesignEnhancer software, is now fully certified for Samsung’s latest process technologies. The Calibre xACT parasitic extraction tool is qualified for Samsung’s multi-bridge-channel FET (MBCFET) technology, an optimized version of gate-all-around (GAA) transistor technology.
  • AI-Powered Custom IC Verification: Siemens’ Solido™ Design Environment and Solido Characterization Suite enhance variation-aware verification and characterization. Solido™ Crosscheck™ ensures comprehensive IP quality assurance.
  • Analog FastSPICE (AFS) Platform: Certified across Samsung’s FinFET, Extreme UltraViolet (EUV), and GAA fabrication processes (SF4X, SF3P, SF2), and the FD-SOI LN18FDS process technology, the AFS platform provides SPICE accuracy and high performance.
  • Open Model Interface (OMI): Supported by Siemens’ AFS platform across Samsung Foundry’s processes from 14nm to 2nm, enabling aging modeling and reliability analysis.

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Optimizing Digital Implementation and Verification

Samsung certified Siemens’ Aprisa™ software for digital implementation for the SF3P process node. This certification ensures customers can design projects at SF3P with fully certified technology, proven correlation with Siemens’ Calibre sign-off tools, and support for Samsung Foundry’s advanced GAA process technology.

Enhanced Power and Design Cycle Efficiency

Siemens and Samsung have developed new design implementation solutions to improve power structure robustness and reduce design cycle time. The Calibre DesignEnhancer, part of Siemens’ Shift Left initiative, automates layout optimization tasks, enhancing design efficiency. It includes:

  • DE Via: Maximizes via insertion to minimize IR drop.
  • DE Pge: Inserts vias and parallel interconnects to optimize power structure and achieve EMIR targets.
  • DE Pvr: Effectively inserts DCAP and Filler cells required for physical verification, saving hours in the design process.

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Advanced IC Test Methodologies

The collaboration has established a new design methodology reference flow. It supports high-quality testing and precise diagnosis for Samsung’s advanced nodes. Built on Siemens’ Tessent™ software, this solution generates comprehensive fault models. It addresses zero DPPM and diagnosis challenges for defects inside cells and interconnects.

Executive Insights

“In today’s fast-paced IC design and fabrication landscape, synergy between partners is essential to meeting the increasingly challenging and complex requirements of our mutual customers,” said Mike Ellow, CEO of Silicon Systems for Siemens Digital Industries Software. “Our collaboration with Samsung Foundry epitomizes this synergy, delivering the power, performance, and area advantages of 3D-IC architectures.”

Sungjae Lee, Vice President and head of Foundry PDK Development Team at Samsung Electronics, added,

Our expanded collaboration with Siemens EDA will help us deliver advanced design enablement solutions that address the evolving needs of our customers. By aligning our roadmaps and optimizing the entire design flow, we can drive advanced packaging innovation across key markets like 5G, automotive, and AI.”

Conclusion

The partnership between Siemens and Samsung Foundry signifies a major leap forward in semiconductor design and manufacturing. By integrating advanced tools and processes, they are poised to meet the increasing demands of high-tech industries, driving innovation and efficiency. This collaboration not only enhances current capabilities but also sets the stage for future technological advancements.

For more information, visit the Siemens website.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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