Introduction:
In today’s AI-driven world, chip performance no longer rests solely on transistor counts or core speeds. Packaging—how the chip is physically assembled and connected—has quietly become a battleground of innovation. And now, an experimental technology out of China is making waves: CoWoP, or Chip on Wafer on PCB.
Promising to remove the expensive substrate layer and mount chips directly onto advanced PCBs, CoWoP is being positioned as a radical cost-saving, performance-boosting alternative to CoWoS (Chip on Wafer on Substrate), the current gold standard.
But is this the next evolution—or just another tech industry hype train?
Let’s break it down and see what’s really going on.
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5 Quick Takeaways:
No Substrates Needed: CoWoP skips ABF substrates, using advanced PCBs instead.
Redefines PCB Roles: PCBs handle signal routing and power distribution, acting like mini-substrates.
Cost Benefits, New Costs: Substrate costs vanish—but high-density PCB requirements raise new ones.
Skepticism from Industry: PCB makers and major chip firms like NVIDIA remain doubtful of its readiness.
Strategic Potential in China: CoWoP fits China’s vision for localized, independent semiconductor ecosystems.
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Background: Why Packaging Now Drives Innovation
Until recently, packaging was an afterthought in chip design. Today, it’s everything. As Moore’s Law slows, companies like TSMC and Intel push performance by integrating multiple chips (chiplets) into one advanced package.
High-bandwidth communication between those chips is critical—especially for large AI models that rely on fast memory access and parallel processing.
That’s where CoWoS shines. Built by TSMC, CoWoS uses an ABF substrate, silicon interposer, and through-silicon vias (TSVs) to connect dies at microscopic scale with high fidelity and power efficiency.
However, CoWoS isn’t perfect:
- ABF substrates are in limited supply.
- Manufacturing is complex and expensive.
- Lead times can stretch months.
This is the problem CoWoP aims to solve—with a bold new approach.
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What is CoWoP? Rethinking the Chip Package
CoWoP flips the traditional model on its head. Instead of bonding chips onto a costly substrate, CoWoP attaches them to an interposer, which is then mounted directly onto a high-density PCB.
The process looks like this:
Step 1: Die-to-Interposer Bonding
Chips are attached to a silicon interposer using micro-bumps, similar to CoWoS.
Step 2: Interposer-on-PCB Assembly
The silicon interposer (with chips on top) is mounted directly onto a multi-layer PCB, built using Modified Semi-Additive Process (mSAP) or High-Density Interconnect (HDI) techniques.
The key here? The PCB isn’t just a board anymore. It acts as the redistribution layer (RDL), routing power and signals just like an ABF substrate would.
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CoWoS vs. CoWoP at a Glance
| Feature | CoWoS | CoWoP |
|---|---|---|
| Substrate | ABF or BT | None (replaced by PCB) |
| Interposer | Silicon | Silicon |
| Final Base | Organic Substrate | Multi-layer HDI/mSAP PCB |
| Cost Structure | High (substrate + complex pkg) | Lower material, higher PCB cost |
| Maturity | Production-proven | Experimental |
| High-End AI Use | Yes | Not yet |
Why PCB Makers Aren’t Celebrating Yet
Infotimes reports that while the concept is appealing, PCB manufacturers are skeptical. CoWoP demands PCBs with sub-10µm line widths and spacing, while most HDI PCBs today are at 20/35µm.
This presents multiple challenges:
- Requires new fab tools and capabilities.
- Raises manufacturing defects and yield issues.
- Adds complexity to PCB design and thermal management.
PCB makers argue that the cost doesn’t disappear—it just shifts. Instead of spending on substrates, companies will need high-performance PCBs, precise micro-bump bonding tools, and new validation cycles.
Why NVIDIA Is Sticking With CoWoS (For Now)
China’s Wallstreetcn reports that top U.S. securities analysts doubt that NVIDIA’s Rubin Ultra, its next-gen AI GPU, will adopt CoWoP.
Why?
- Rubin Ultra demands larger substrates and more RDL layers than ever.
- CoWoP PCBs can’t currently support the bandwidth and thermal limits needed for AI workloads.
- A switch would force NVIDIA to overhaul its entire packaging, supply chain, and QA process.
Until CoWoP proves it can match CoWoS in signal integrity, power delivery, and reliability, major AI players will likely stay away.
Where CoWoP Could Shine First
CoWoP might not be ready for data centers—but it has strong potential in low-to-mid-range applications, such as:
- Smartphones and tablets
- IoT chipsets
- Edge AI accelerators
- Consumer electronics
These applications value:
- Lower power consumption
- Cost-effectiveness
- Faster time to market
In these segments, CoWoP can offer a strategic edge by simplifying packaging steps and avoiding substrate bottlenecks.
A Geopolitical Angle: China’s Strategic Bet on CoWoP
Another reason CoWoP is gaining buzz in China? Supply chain independence.
U.S. sanctions limit access to high-end substrates, chip packaging tools, and EDA software. CoWoP allows Chinese firms to bypass global substrate dependencies and rely more on domestic PCB and packaging talent.
Even if CoWoP doesn’t conquer the global AI chip market, it could become a pillar of China’s “localization” push in semiconductors.
Conclusion:
CoWoP introduces a fresh vision in semiconductor packaging—cost-efficient, streamlined, and substrate-free. But transforming vision into reality requires time, trust, and tooling.
CoWoP won’t replace CoWoS overnight. Still, it’s not just hype. Like any radical new idea, it challenges conventions and forces us to think differently.
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