High-NA EUV Dilemma: Why TSMC and Intel Are Taking Different Paths with ASML

TSMC claims they can produce the next-generation A16 without High NA technology, while Intel has reserved the capacity for the next year. Whose bet might pay off?

Introduction:

In the ever-evolving landscape of semiconductor manufacturing, the decisions made by industry giants like TSMC often have far-reaching implications. Recently, TSMC executive Kevin Zhang hinted at the possibility of bypassing ASML (Advanced Semiconductor Materials Lithography) next-generation “High NA EUV” machines for their upcoming A16 chips manufacturing technology.

Why it matters: These high-tech machines are supposed to be a game changer, shrinking chip designs significantly. But there are drawbacks.

The drawbacks: They’re super expensive (think hundreds of millions per machine) and their reliability is unproven compared to current tech.

TSMC’s approach: They’re confident they can achieve sufficient performance for the A16 using existing technology, focusing on a balance between cost and effectiveness.

The future: While they might not use the new machines for A16, TSMC is open to using them later if the economics and technical aspects make sense.

This decision, if realized, could signal a significant shift in the dynamics of chip production technology. Let’s delve deeper into the intricacies of this development and its potential implications.

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TSMC Quest for Advanced Chip Manufacturing without ASML NA EUV:

Chipmakers continually strive to push the boundaries of innovation, seeking ways to produce chips that are smaller, faster, and more energy-efficient. Central to this endeavor is the field of lithography, which plays a pivotal role in defining the features and intricacies of semiconductor chips.

ASML, as a leader in lithography systems, has been at the forefront of providing cutting-edge technologies to chip manufacturers worldwide.

High-NA EUV lithography is expected to achieve a resolution around 8nm. This is a significant improvement compared to the current standard EUV lithography which can reach around 13nm.

Current EUV: With a numerical aperture (NA) of 0.33, current EUV lithography can print features with a minimum pitch (distance between identical features) of around 13nm.

High-NA EUV: By increasing the NA to 0.55, High-NA EUV can achieve a smaller minimum pitch, estimated to be around 8nm. This translates to the ability to print features that are 1.7 times smaller compared to standard EUV.

It’s important to note that reaching 8nm resolution is not just about the increased NA. High-NA EUV systems also incorporate other advancements to achieve this feat. These include:

Anamorphic Lenses: These specialized lenses use different magnification ratios in different directions to compensate for limitations arising from the higher NA.pen_spark

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The High NA EUV Dilemma from ASML: TSMC vs. Intel

The recent news of TSMC’s decision to potentially forgo ASML’s latest High-NA EUV machines for their A16 chip generation has sparked a debate in the chipmaking industry. Here’s a breakdown of the situation and its implications for both TSMC and Intel:

TSMC’s Strategy:

TSMC

TSMC Process node Roadmap

Focus on Existing Technology: TSMC believes they can achieve sufficient performance for the A16 using current EUV technology and other advancements. This approach prioritizes cost-effectiveness while still achieving innovation.

Potential Alternatives: They might explore alternative lithography techniques like nanoimprint lithography, although its maturity is a concern.

Reasons for TSMC’s Skepticism:

High Cost: The hefty price tag (potentially over €350 million per machine) makes High-NA EUV a significant investment.

Reliability Concerns: The technology is relatively new, and its long-term reliability compared to established methods remains unproven.

I like the technology but I don’t like the sticker price.. When actually High NA EUV will come in play, I think it depends on where’s the optimum economic and the technical balancing we can achieve.

~Kevin Zhang, TSMC Executive

Impact on TSMC:

Maintaining Dominance: This wait-and-see approach could potentially slow down their progress in shrinking chip size compared to Intel, who has embraced High-NA EUV.

Future Flexibility: TSMC remains open to adopting High-NA EUV if the economics and technology mature in the future.

Intel’s Strategy:

ASML Ships to Intel
ASML Shipping to Intel is a big deal

Early Adoption: Intel has reportedly secured all of ASML’s High-NA EUV machines allocated for 2024. They aim to be the first to leverage this technology for their future chip generations.

TSMC was the forerunner in adopting EUV lithography in the 2010s. This gave them a significant head start in experience and expertise with this advanced technology.

Potential Risks: Being an early adopter comes with risks. The high cost and unproven reliability of High-NA EUV could lead to unforeseen challenges.

Impact on Intel:

Potential Leadership: If successful, Intel could regain chip manufacturing leadership from TSMC.

Financial Burden: The hefty upfront cost of the machines could put a strain on Intel’s finances.

Industry Implications:

TSMC’s decision sets a precedent: Other chipmakers might follow suit, impacting ASML’s sales of High-NA EUV machines in the short term.

Pressure on ASML: This could push ASML to refine their technology and pricing strategy to make High-NA EUV more attractive.

TSMC’s proven track record with EUV makes their decision to hold off on High-NA EUV more calculated. They might be confident in their ability to optimize current technology for A16. Intel’s lack of experience with EUV adds another layer of risk to their High-NA EUV gamble. They might face unforeseen challenges integrating and utilizing this new technology.

This situation highlights the complex trade-offs in chipmaking. TSMC prioritizes a balanced approach, while Intel takes a more aggressive gamble on cutting-edge technology. Only time will tell which strategy proves more successful in the long run.

Implications for the Semiconductor Landscape:

TSMC’s stance on High NA EUV technology reverberates throughout the semiconductor ecosystem.

TSMC’s position as the leading contract chipmaker gives it considerable influence.
Being a major customer of ASML further enhances its impact.

If TSMC decides against High NA tools, it could shape the strategies of other chipmakers.
Its decision may set a precedent for the industry’s approach to chip manufacturing.

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Conclusion:

TSMC’s potential decision to bypass ASML’s High NA EUV machines is under intense deliberation.

This highlights the intricate balance between innovation, economics, and strategic planning in the semiconductor sector.

The choice of lithography systems is critical for chipmakers shaping the industry’s future.

TSMC’s decisions will have far-reaching effects, shaping competition and technological progress.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Priyadarshi is a prominent figure in the world of technology and semiconductors. He is the founder of Techovedas, India’s first semiconductor and AI tech media company, where he shares insights, analysis, and trends related to the semiconductor and AI industries.

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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