Verification Engineer
A design verification engineer plays a crucial role in the development of electronic systems, particularly in the semiconductor industry. Their primary responsibility is to ensure that a design meets its specifications and functions correctly before it is manufactured.
As a verification Engineer, You will be responsible for creation of “state of the art” UVM based verification test benches and methodologies to verify complex IP’s/Sub-systems/SOC’s.
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Responsibilities:
- Develop test plans, tests and verification infrastructure for complex IP’s/sub-system/SOC’s
- Create verification environment using UVM methodology
- Create reusable bus functional models, monitors, checkers and scoreboards
- Drive functional coverage driven verification closure
- Work with architects, designers and post-silicon teams.
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Skill Sets:
- BTech/ MTech with 3+ years of experience
- Unit/Sub-system/SOC level verification experience
- Experience in at least one of the following areas:
o CPU verification, Memory controller verification, Interconnect verification
o High Speed IO verification (UFS/PCIE/ XUSB)
o Graphic processing units
o Bus protocols (AXI/APB)
o Formal verification - Experience in leading verification closure of complex IP/SOC for at least one project
- Experience in verification methodologies like UVM/VMM
- Exposure to industry standard verification tools for simulation and debug
- Good debugging and problem solving skills.
- Good communication skills and ability & desire to work as a team player
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