Hiring: RTL Design Engineer

In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver afully verified, synthesis/timing clean design.

Introduction:

An RTL (Register-Transfer Level) design engineer is a professional who specializes in the design and development of digital circuits at the register-transfer level of abstraction. This role involves defining the behavior and structure of digital circuits using hardware description languages (HDLs) such as VHDL (VHSIC Hardware Description Language) or Verilog.

In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver afully verified, synthesis/timing clean design. You will work with architects, other designers, pre- andpost-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.

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What You’ll Be Doing:


Own micro-architecture and RTL development of design modules.
Micro-architect features to meet performance, power and area requirements.
Work with HW architects to define critical features.
Collaborate with verification teams to verify the correctness of implemented features.
Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface
requirements and is routable.
Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
Work on post-silicon verification and debug.

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What We Need To See

BS / MS or equivalent experience.
3+ years of design experience.
Experience in RTL design of complex design units for at least two or three projects.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy,
GDB).
Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,
DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Expertise in Verilog.

Ways To Stand Out From The Crowd

Design experience in memory subsystem or network interconnect IP.
Good debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).

Apply here

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