How Did TSMC Really Slash EUV Power by 50% Without Risking Chips?

How did TSMC cut EUV power by 50% without risking chip yields? Discover their Dynamic Energy Saving Program, projected savings, and industry impact.

Introduction

Taiwan Semiconductor Manufacturing Company (TSMC), the world’s leading chip foundry, has achieved a remarkable feat: slashing the power consumption of its extreme ultraviolet (EUV) lithography systems by nearly 50%, all without affecting chip yield or throughput.

This milestone was revealed through TSMC’s Dynamic Energy Saving Program, launched at several core fabs in Taiwan, including Fabs 15B, 18A, and 18B, in September 2025. The company plans a global rollout across all EUV tools by the end of the year, including integration in new facilities like Fab 21 Phase 2 in Arizona.

The semiconductor industry is watching closely. If TSMC’s approach proves scalable, it could reshape energy consumption standards for advanced chip manufacturing worldwide.

5 Key Points at a Glance

Dynamic Energy Saving Program: TSMC targets energy-intensive EUV lithography systems.

Nearly 50% reduction in peak power achieved without compromising chip yields or production quality.

Global rollout: Program extending to all EUV tools and new fabs, including Fab 21 Phase 2 in Arizona.

Massive projected savings: 190 million kWh electricity and 101,000 tons of CO₂ by 2030.

Industry impact: Shows a scalable path to sustainable, energy-efficient semiconductor production.

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How the Program Likely Works

TSMC has not publicly disclosed detailed technical steps, but analysts suggest the program relies on adaptive, real-time energy management. Key strategies likely include:

  • Idle power reduction: EUV scanners draw full power only when wafers are being exposed.
  • Flexible production scheduling: Coordinating wafer flow to avoid energy spikes.
  • Cleanroom data integration: Tools communicate in real-time to optimize energy across the production line.

Interestingly, TSMC hints that the program could extend to deep ultraviolet (DUV) scanners and other fab equipment, signaling a broader push for energy-efficient semiconductor manufacturing.

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Impressive Results Without Compromising Yields

EUV lithography is among the most energy-intensive processes in chip manufacturing. Last year, TSMC reported a 25% reduction in energy use through internal redesigns and fab-wide automation.

The new program goes even further. By leveraging real-time monitoring and adaptive energy control, TSMC has cut peak power draw by up to 44%, all while maintaining:

  • Production throughput – wafers per hour remain unaffected.
  • Chip quality – no increase in defects.
  • Process stability – critical for cutting-edge logic chips.

This combination of efficiency and reliability is rare in semiconductor manufacturing, where energy reductions often come at the expense of output.

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Global Rollout and Future Plans

The rollout began in Taiwan, but TSMC plans to extend it to all EUV tools worldwide by the end of 2025. The program will also become standard in new fabs, ensuring that future facilities are energy-efficient from day one.

Projected impact by 2030:

  • Electricity savings: 190 million kWh, roughly equivalent to powering 55,000 homes for a year.
  • CO₂ reduction: 101,000 tons, aligning with global sustainability goals.
  • Cost savings: About NT$22.44 million annually in electricity expenses.

These figures highlight that even incremental improvements in tool efficiency can produce substantial environmental benefits, especially at a company of TSMC’s scale.

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Energy Consumption in Context

Despite these gains, TSMC’s total energy usage remains immense. In 2024:

  • Total electricity consumed: 25.55 billion kWh.
  • Renewable energy share: Only 3.61 billion kWh.
  • Share of Taiwan’s total demand: ~9%.

Interestingly, less than half of this energy went to lithography and process tools; the remainder supported cleanrooms, cooling, and air conditioning, which are critical for maintaining chip quality.

TSMC’s program addresses wasted energy in the tools themselves, tackling a portion of the footprint but leaving opportunities for broader energy-saving initiatives in fab infrastructure.

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Why This Matters for the Semiconductor Industry

TSMC’s approach has several important implications:

  1. Industry benchmark: As the largest chip foundry, TSMC sets standards for energy efficiency that competitors may follow.
  2. Sustainability: Reducing 101,000 tons of CO₂ aligns with ESG goals and growing regulatory pressure.
  3. Operational cost reduction: Energy efficiency translates into long-term savings.
  4. Scalable technology: Adaptive energy control could be applied to DUV scanners and other high-energy tools.
  5. Innovation leadership: Shows that leading-edge manufacturing can be both high-performance and environmentally responsible.

Related Moves in the Industry

Other semiconductor companies are exploring energy efficiency and sustainability:

  • Intel is discussing optimized chip production for AMD in its fabs.
  • Global foundries increasingly use real-time energy management systems to reduce peak power.
  • Government-supported chip programs emphasize sustainable semiconductor production as a strategic priority.

TSMC’s program is a clear signal that energy-efficient manufacturing is no longer optional—it’s becoming an industry necessity.

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Conclusion:

TSMC’s Dynamic Energy Saving Program demonstrates that dramatic energy reductions are possible without compromising chip quality or yields. By cutting nearly half of EUV power consumption, TSMC is proving that sustainability and high-tech manufacturing can coexist.

TSMC’s approach is a model for the future of chipmaking: efficient, sustainable, and highly innovative—a combination that could reshape global semiconductor manufacturing in the coming decade.

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Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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