Understanding Semiconductor Yields: The Role of Defect Density and Die Size
In the world of advanced semiconductor manufacturing, yields—often a critical metric—are influenced by several key factors, notably defect density and die size. Recent discussions around Intel’s 18A node and TSMC’s 2nm technology have reignited conversations about what yield percentages really mean and how they should be interpreted. Let’s break it down.
What Is Yield in Semiconductor Manufacturing?
Yield refers to the proportion of functional chips produced from a wafer during semiconductor fabrication. However, speaking about yield solely in terms of percentages can be misleading. Two critical variables come into play:
- Defect Density (Defects per cm²):
- This measures the number of defects in a given area of the wafer. Lower defect density means fewer chances of defects ruining a die, leading to higher yields.
- Die Size:
- Larger dies are statistically more likely to encounter defects because of their greater surface area. Conversely, smaller dies are less likely to overlap with defect spots, resulting in higher yields.
The interplay between these two factors underscores why “yield as a percentage” needs proper context, as highlighted by Intel’s former CEO in a recent Twitter exchange.
Intel’s 18A Node: Yield and Defect Density
Intel’s 18A node, its most advanced process to date, has been reported to have a defect density of below 0.4 defects per cm² as of September 2024. This is a promising achievement for a cutting-edge node still in its early stages of optimization.
To illustrate how die size influences yield:
- A 600mm² die (typical of high-performance GPUs or server CPUs) with a defect density of 0.4 defects/cm² yields 14% functional dies under the Murphy yield model, a widely accepted statistical model for calculating semiconductor yields.
- A much smaller 115mm² die (comparable to Intel’s Arrow Lake compute tile) on the same node yields 64% functional dies under the same conditions.
The discrepancy arises because larger dies cover more wafer area, increasing the likelihood of intersecting defect spots.
The Mathematics of Yield: A Simplified Example
Imagine a wafer with 100 potential dies and 50 defect spots:
- Large Dies: A large die that spans a significant portion of the wafer could overlap with multiple defects, making most of the large dies unusable.
- Small Dies: Smaller dies create a kind of “quarantine effect,” where defects are isolated to fewer chips. With the same number of defect spots, many more small dies remain unaffected and functional.
This dynamic is why smaller dies inherently achieve higher yield percentages than larger ones on the same node and wafer.
TSMC’s 2nm Yields vs. Intel’s 18A
In a recent tweet, Dan Nystedt, a technology Journalist noted that TSMC’s 2nm process achieved over 60% yield in trial production. While impressive, the size and type of dies used in this calculation remain unclear. Intel’s ex-CEO, Pat Gelsinger aptly pointed out that without specifying die size, such percentages lack meaningful context.
https://x.com/dnystedt/status/1864983385363689550
Image Credits: X/Dan Nystedt
TSMC’s 2nm is also significant as it introduces nanosheet transistors—a more complex technology than the FinFET transistors used in its 3nm process. Similarly, Intel’s 18A features RibbonFET transistors and PowerVia, two advanced technologies enabling smaller, more efficient chips.
Implications for the Industry
- Intel’s 18A Node:
- While 18A yields for large dies might currently hover around 10-14%, this is acceptable for early-stage production.
- For smaller dies, such as those used in consumer products, yields are already at a workable level (~64%).
- As defect densities improve with process maturity, 18A will become increasingly attractive to both Intel and potential foundry customers.
- TSMC’s 2nm Node:
- With trial production yields reportedly above 60%, TSMC demonstrates its leadership in nanosheet transistor technology.
- However, like Intel, these numbers are likely driven by small, test-oriented dies, which may not reflect yields for larger, commercial designs.
The Path Forward: Continuous Optimization
Yield improvement is an iterative process. Both Intel and TSMC are expected to refine their defect densities and manufacturing techniques over time. Intel’s 18A, in particular, has room to grow, as seen with previous nodes that started with lower yields and reached maturity over several quarters.
Conclusion: Interpreting Yield with Context
The discussion about semiconductor yields underscores the importance of looking beyond raw percentages. By focusing on defect density and die size, a more nuanced picture emerges, enabling better understanding of the challenges and opportunities in advanced semiconductor manufacturing.
For Intel, 18A may not yet appeal to customers building massive dies, but for smaller designs, it is already competitive. TSMC’s 2nm process, meanwhile, continues to set benchmarks for nanosheet technology, though its applicability to larger dies remains to be seen.
As the race for advanced nodes continues, both companies are pushing the boundaries of what’s possible, setting the stage for a new era in semiconductor innovation.
