How Hoerni’s Planar Process led to a Semiconductor Manufacturing Revolution

Focused on getting its first devices into production, the company did not pursue the approach at that time. Due to concerns about possible contaminants, conventional wisdom required removing this layer after completion of oxide masking, thus exposing the junctions.
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Jean Hoerni idea doesn’t find a taker in Fairchild

On December 1, 1957, physicist Jean Hoerni documented a novel idea in his patent notebook on page 3-4 at Fairchild Semiconductor in Palo Alto, California. This idea revolved around safeguarding exposed p-n junctions on silicon transistors using oxide masking techniques. This concept marked the inception of the planar process, a groundbreaking transistor design that preserved the oxide layer on the silicon wafer to shield the delicate p-n junctions beneath it. However, at that time, Fairchild Semiconductor was primarily focused on getting its initial semiconductor devices into production and did not pursue Hoerni’s planar approach.

Traditionally, it was believed that the oxide layer should be removed after the oxide masking process due to concerns about potential contaminants, thereby exposing the junctions. In contrast, Hoerni saw the oxide layer as a potential solution. His “planar” approach, named after the flat topography of the final device, aimed to protect these junctions. Two years later, this concept became a crucial component in the manufacturing of Robert Noyce’s 1959 invention of the first commercially produced monolithic integrated circuit, which forms the foundation of nearly all contemporary semiconductor manufacturing. Consequently, Hoerni did not draft a patent disclosure for what ultimately became U.S. patent 3025589 until January 1959.

Fairchild Notebook of Joen Hoerni,1957.

Image Credits: Computer history Archive

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Jean Hoerni was part of Famous Traitorous 8

Jean Hoerni was born on September 26, 1924, in Geneva, Switzerland. He earned a B.S. in Mathematics from the University of Geneva. Hoerni pursued two Ph.D.s in Physics, one from the University of Geneva and another from the University of Cambridge. In 1952, he moved to the United States to work at the California Institute of Technology. There, he met William Shockley, a physicist at Bell Labs deeply engaged in transistor invention.

A few years later, Shockley brought Hoerni into the newly established Shockley Semiconductor Laboratory division of Beckman Instruments in Mountain View, California. However, Shockley’s unusual behavior led Hoerni and the “traitorous eight” (comprising Hoerni, Julius Blank, Victor Grinich, Eugene Kleiner, Jay Last, Gordon Moore, Robert Noyce, and Sheldon Roberts) to depart from Shockley’s laboratory and establish Fairchild Semiconductor corporation.

In 1958, at an Electrochemical Society meeting, Hoerni saw Mohamed Atalla’s paper. Atalla discussed using oxide to passivate p-n junctions, highlighting silicon dioxide’s protective role. Hoerni found this intriguing. He began contemplating Atalla’s device and came up with the idea of planar technology. Hoerni wanted to use silicon dioxide to protect the silicon surface in transistors.

Read more: The Curse of Shockley: How Toxic Leadership Sparked a Technological Revolution

The planar process of Jean Hoerni

The inception of the planar process is credited to Jean Hoerni, and he filed its initial patent in May 1959. This breakthrough played a pivotal role in the development of the Silicon Integrated Circuit by Robert Noyce. Noyce expanded upon Hoerni’s contributions by conceptualizing an integrated circuit that involved adding a layer of metal atop Hoerni’s fundamental structure. This additional metal layer facilitated the interconnection of various components like transistors, capacitors, or resistors, all situated on a single piece of silicon.

The planar process revolutionized the implementation of integrated circuits, surpassing earlier conceptions of the device in terms of efficiency and effectiveness. While Jack Kilby from Texas Instruments is commonly associated with the invention of the integrated circuit along with Noyce, Kilby’s IC was based on Germanium. However, Silicon ICs proved to have numerous advantages over their Germanium counterparts. This significance of silicon in the realm of integrated circuits is encapsulated in the term “Silicon Valley.”

Before the planar process, making electronic components like transistors on silicon was like building on bumpy terrain. It was hard to protect the sensitive parts and connect them well. Imagine constructing a house on a rough, uneven ground—it’s tricky to keep everything stable and connected.

The planar process was like laying a smooth foundation before building. It provided a flat surface (like a solid foundation for a house) on which electronic components could be placed and connected easily. This made it much simpler to protect these components and link them together effectively, like building a sturdy house on a smooth, stable base. In essence, the planar process made producing and connecting electronic parts much more efficient and reliable.

Read more: History of VLSI: Transistor to System-on-a-Chip

Planar process led to development of first Integrated Circuit

Jean Hoerni, in addition to inventing the planar process, actively advocated for its benefits and applications. The invention stemmed from efforts to address surface irregularities in semiconductor devices. By employing the planar process, Hoerni achieved a stable surface for semiconductor components, enhancing their reliability for use in extensive systems.

Initially, the planar transistor found significant application in military systems, proving its reliability through tests such as those for Minuteman. This invention was foundational for the practical realization of integrated circuits and has since become a standard in transistor manufacturing. The planar transistor’s structure had an inherent oxide coating. This coating acted as a vital insulating film. It allowed smooth interconnection of transistors in integrated circuits.

This breakthrough brought about a notable enhancement in reliability and cost reduction for computer components. Moreover, the stable insulator introduced by the planar process made MOS (Metal-Oxide-Semiconductor) devices a feasible and practical option.

Image Credits: US patent office

The planar devices exhibited superior electrical properties, notably significantly reduced leakage currents, a crucial aspect in computer logic design. They enabled manufacturing of all IC components from a single side of a wafer, a significant milestone in 1960.

Fairchild led by commercially introducing the 2N1613 planar transistor in April’60 and widely shared the rights to this process throughout the industry.

Today’s billion-transistor integrated circuits owe their existence to Hoerni’s pioneering concept. A historian has even labeled it as

“the most pivotal innovation in the entire history of the semiconductor industry.”

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