Imec Unveils Industry-First Design Pathfinding PDK for N2 Node

This innovative initiative, coupled with a comprehensive training program through EUROPRACTICE, promises to revolutionize the landscape of chip design by providing academia and industry with early access to advanced node

Introduction:

In a groundbreaking move aimed at democratizing access to cutting-edge semiconductor technologies, imec, a global leader in nanoelectronics and digital innovation, unveiled its open Process Design Kit (PDK) during the 2024 IEEE International Solid-State Circuits Conference (ISSCC).

This innovative initiative, coupled with a comprehensive training program through EUROPRACTICE, promises to revolutionize the landscape of chip design by providing academia and industry with early access to advanced nodes, fostering innovation, and nurturing the semiconductor experts of tomorrow.

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Breaking Down the Initiative:

Traditionally, access to Foundry PDKs—essential for chip designers—has been limited and gated behind NDAs, posing significant barriers for both academia and industry to explore and develop on advanced technology nodes.

However,Imec’s N2 PDK aims to dismantle these barriers by offering an open platform embedded in leading Electronic Design Automation (EDA) tool suites from industry giants like Cadence Design Systems and Synopsys.

This move ensures broad accessibility to advanced nodes, enabling designers to embark on meaningful design pathfinding, system research, and training.

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Features of the Design Pathfinding PDK:

The imec N2 PDK encompasses a comprehensive infrastructure tailored for digital design, featuring a rich library of tested and proven components, including digital standard cell libraries and SRAM IP macros.

This platform not only facilitates the development of functional and reliable designs but also lays the groundwork for future advancements, with plans to extend support to more advanced nodes like A14 in the pipeline.

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Accelerating Learning Through Training Programs:

Recognizing the pivotal role of education in shaping the semiconductor workforce of the future, imec, in collaboration with EUROPRACTICE, is set to roll out a comprehensive training program starting in early Q2.

Moreover,this program will equip subscribers with in-depth knowledge of the N2 technology node and provide hands-on training using Cadence and Synopsys EDA software.

By bridging the gap between academia and industry, these courses aim to cultivate a skilled workforce capable of driving semiconductor innovation forward.

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Industry Partnerships Driving Innovation:

The launch of imec’s design pathfinding PDK has garnered enthusiastic support from industry leaders, underscoring the collaborative effort to broaden access to advanced process technology.

Additionally,Synopsys and Cadence, two prominent players in the EDA space, have hailed imec’s initiative as a catalyst for accelerating semiconductor innovation.

These companies are ready to help design teams create prototypes and smoothly switch to new technologies by teaming up strategically and using AI-driven design processes.

Looking Ahead:

Imec’s open PDK and training program are important for guiding the direction of the semiconductor industry as it changes quickly.

By democratizing access to advanced nodes and fostering a culture of collaboration and education, imec is not only empowering the current generation of chip designers but also laying a solid foundation for the semiconductor innovations of tomorrow.

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Conclusion:

In an era defined by technological disruption and innovation, imec’s launch of the open Process Design Kit (PDK) marks a significant milestone in the journey towards democratizing access to advanced semiconductor technologies.

Moreover, providing academia and industry with the tools and knowledge needed to navigate the complexities of chip design, imec is paving the way for a future where innovation knows no bounds.

As we embark on this transformative journey, let us embrace the spirit of collaboration, education, and empowerment, driving semiconductor innovation to new heights.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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