InCore Unveils Six-Core RISC-V Test Chip to Accelerate Design Adoption

By integrating multiple core variations on a single die, InCore aims to streamline the development process, enabling faster time-to-market for clients.

Introduction

InCore Semiconductors has launched a cutting-edge six-core RISC-V test chip, marking a significant advancement in semiconductor technology.

This innovative chip utilizes the company’s proprietary generator technology, allowing for flexible architecture tailored to various applications, such as Brushless DC (BLDC) motors and smart-card systems.

It’s Just the Beginning: Semiconductor Industry Leaders Applaud PM Modi’s Vision | by techovedas | Sep, 2024 | Medium

Introduction: Revolutionizing RISC-V Technology

The six-core RISC-V test chip is set to redefine how developers approach system-on-chip (SoC) design.

By integrating multiple core variations on a single die, InCore aims to streamline the development process, enabling faster time-to-market for clients.

This move aligns with the growing demand for adaptable and efficient semiconductor solutions in a rapidly evolving tech landscape.

Key Features of the Six-Core RISC-V Test Chip

  1. Flexible Architecture: Utilizes proprietary generator technology to customize core instantiation for specific applications.
  2. Multiple Core Variations: Incorporates two core generators—Azurite and Calcite—enabling automation of core instantiation.
  3. Seamless Functionality Switching: Designed to allow users to switch between functionalities, similar to ARM’s M0, M1, and M2 cores.
  4. Integration with Security IPs: The chip integrates multiple security intellectual properties (IPs) and peripherals for enhanced functionality.
  5. Support for Emerging Technologies: Positions InCore to engage with startups under the Design-Linked Incentive (DLI) program, focusing on market needs and innovation.

Lam Research Expands Virtual Semiconductor Training to 20 Indian Universities, Aiming to Upskill 60,000 Engineers — techovedas

Insights from InCore’s CTO

In an exclusive interview with EFY, InCore’s Chief Technology Officer, Neel Gala, elaborated on the chip’s development process.

The team utilized their two core generators—Azurite and Calcite—to create multiple core variations, demonstrating the reliability of their technology through an internal test chip.

“In response to customer inquiries regarding the stability of our technology, we automated the instantiation of four different Azureites and two Calcites. This automation streamlines the development process, essential for accelerating time-to-market for our clients.”

Gala stated,

This focus on reliability is crucial for establishing trust among potential users and partners.

Demonstration at SEMICON India

At the recent SEMICON India event, InCore showcased the capabilities of the six-core RISC-V test chip, running Zephyr OS—an industry first in the RISC-V ecosystem. Gala emphasized the significance of this demonstration, saying, “By creating multiple cores with equivalent specifications on a single die, we allow users to switch functionalities seamlessly.” This flexibility can enhance product performance and user experience in various applications.

Strategic Partnerships and Market Engagement

The introduction of the six-core RISC-V chip is part of InCore’s broader strategy to collaborate with startups under the DLI program.

This initiative is designed to identify market needs and support innovative projects that address emerging technology trends.

Last year, InCore partnered with a major DLI-supported company to develop energy meter products aimed at large-scale adoption in the Indian market. Gala remarked, “We expect to help them navigate price competition in a saturated market.” This strategic partnership highlights InCore’s commitment to fostering innovation while tackling real-world challenges.

Additionally, InCore is collaborating with another startup focused on AI chips for telecommunications and 5G/6G applications. These partnerships are pivotal in driving RISC-V adoption and enabling unique product development across diverse sectors.

Support for Startups through the DLI Program

The DLI program has proven instrumental in providing startups access to Electronic Design Automation (EDA) tools through government partnerships with leading vendors like Synopsys and Cadence.

This support alleviates the financial burden of expensive tools, allowing startups to concentrate on product development.

InCore’s engagement with the DLI program reflects its dedication to enhancing the semiconductor ecosystem in India. By refining policies and improving accessibility for startups, InCore aims to drive RISC-V adoption and support advancements in home automation, smart devices, and next-generation computing.

Conclusion: A New Era for RISC-V

InCore’s unveiling of the six-core RISC-V test chip represents a significant milestone in semiconductor innovation.

The chip’s flexible architecture supports diverse applications. It accelerates design adoption while positioning InCore as a leader in the RISC-V ecosystem.

As demand for adaptable semiconductor solutions grows, InCore’s focus on innovation is crucial. Their collaboration will be key in shaping the future of technology.

By leveraging proprietary technology and engaging with startups, InCore is well-equipped to navigate the challenges of a dynamic market.

The future looks promising for RISC-V technology, and InCore is at the forefront of this revolution.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Priyadarshi is a prominent figure in the world of technology and semiconductors. With a deep passion for innovation and a keen understanding of the intricacies of the semiconductor industry, Kumar has established himself as a thought leader and expert in the field. He is the founder of Techovedas, India’s first semiconductor and AI tech media company, where he shares insights, analysis, and trends related to the semiconductor and AI industries.

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. He couldn’t find joy working in the fab and moved to India. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL)

Articles: 2237