Is Moore's Law Dead ft. TSMC SVP Kevin Zhang Answers

Introduction

In an exclusive interview with TechTechPotato, Dr. Kevin Zhang, Senior Vice President at TSMC, shared insights on the state of Moore’s Law, the company’s incremental technology strategy, and future innovations.

The conversation covered TSMC’s approach to semiconductor scaling, the impact of emerging technologies like chiplets and advanced packaging, and the company’s plans for high-performance computing and AI applications.

Moore’s Law is the observation made by Gordon Moore, co-founder of Intel, in 1965. It states that the number of transistors on a microchip doubles approximately every two years, leading to an exponential increase in computing power and a decrease in cost per transistor. This principle has driven the rapid advancement of semiconductor technology and innovation in the tech industry.

Is Moore’s Law Dead?

The debate over Moore’s Law’s relevance continues, with some industry leaders claiming it’s dead due to diminishing returns from traditional two-dimensional scaling.

4 Reasons why Moore’s Law Might be Dead, Finally!

However, Dr. Zhang offers a different perspective. “As long as we can continue to drive technology scaling, I don’t care if Moore’s Law is alive or dead,” he stated.

TSMC’s focus is on integrating more functions and capabilities into smaller form factors, ensuring higher performance and power efficiency.

This shift from traditional definitions suggests that while Moore’s Law in its original sense may be challenged, the spirit of innovation it embodies is very much alive.

Rs 21,936.90 Crore: MeitY Secures Major Budget Increase 52% Boost in FY 2024-25 – techovedas

TSMC’s Incremental Strategy: A Recipe for Success

TSMC is renowned for its incremental advancements in process node technology. Dr. Zhang emphasized that these “incremental” steps are substantial, offering significant energy efficiency improvements.

For example, transitions from 5nm to 3nm nodes involve over 30% improvements in power, performance, and density.

This strategy allows customers to maximize their investments by continuing to leverage enhancements within each major node, such as moving from N5 to N5P or N4 to N4P.

These incremental improvements enable customers to achieve scaling benefits without incurring the high costs associated with jumping to entirely new nodes.

NVIDIA and Thapar Launch Advanced AI & Data Science School in India – techovedas

The Growing Demand for Compute Power and the Future of Packaging

The demand for energy-efficient computing power shows no signs of slowing down. TSMC emphasizes that as technology advances, the appetite for compute power remains insatiable. For instance, AI models like ChatGPT and GPT-4 already rely heavily on training chips, driving the need for even more advanced technology.

TSMC is committed to expanding its capabilities at the transistor level, with plans to advance from 3nm to 2nm technology. The upcoming A16 node will further enhance energy-efficient computing. Simultaneously, TSMC is advancing wafer-scale packaging with CoWoS (Chip-on-Wafer-on-Substrate) technology and integrating optical signaling into its packages. This comprehensive approach aims to provide customers with the ability to integrate more compute functions and memory bandwidth, addressing the growing requirements of future AI applications.

Innovations in Packaging and New Technologies

TSMC is not just focused on process nodes but also on revolutionary packaging technologies. The introduction of Nanosheet transistors and backside power rail design in the A16 node represents a significant leap in semiconductor technology.

The backside power rail design moves power supply routing from the front to the back, enhancing performance and power efficiency, particularly critical for high-performance systems like AI and HPC.

Dr. Zhang also discussed the CoWoS (Chip-on-Wafer-on-Substrate) technology, which is essential for AI accelerators.

TSMC is expanding CoWoS capacity and capability, with plans to support up to 12 HBM (High Bandwidth Memory) stacks in the near future.

Furthermore, TSMC is exploring System on Wafer technology, which could allow for unprecedented levels of integration and compute power.

Google and MeitY to Fuel 10,000 Indian Startups with $350,000 in AI Cloud Credits – techovedas

Dr. Zhang on High-NA EUV: TSMC’s Position and Future Outlook

Regarding high-NA EUV, Dr. Zhang reaffirmed TSMC’s leadership in EUV technology. “Let’s take a step back,” he said. “TSMC was the first to bring EUV into high-volume manufacturing with our 7-nanometer process. We continue to lead in both the application of EUV and production efficiency.”

Dr. Zhang emphasized that TSMC’s R&D team is actively evaluating new EUV capabilities, including high-NA EUV. “We are carefully considering where to integrate this next-generation technology. There are many factors at play, including scalability and manufacturing costs,” he explained. “I have confidence that our R&D team will make the most informed decision on when and where to adopt high-NA EUV for future technology advancements.”

Future Directions and Global Expansion

TSMC continues to innovate in the realm of optical technologies as well. The Compact Universal Optical Engine (CoUPE) is a major advancement in silicon photonics.

It enables more efficient data transfer. It also reduces power consumption. This technology could play a crucial role in future data center and AI applications.

Regarding global expansion, TSMC is rapidly increasing its manufacturing footprint. New fabs are being built in Arizona, Japan, and Europe.

They focus on advanced nodes and specialty technologies. These expansions aim to meet growing global demand. They ensure a more distributed supply chain. They also enhance supply chain resilience.

AMD Unveils AI Beast Ryzen AI 9 HX 375 in a Quiet Update to its Lineup – techovedas