Introduction
For decades, semiconductor design has balanced between creativity and complexity. Chip architects draft specifications, engineers interpret them line by line, and verification teams spend months writing and debugging thousands of lines of Verilog and UVM code. But that balance is shifting. Moores Lab(AI), a startup founded by veterans of chip engineering and artificial intelligence, believes it’s time to end the “manual everything” era.
The company is pioneering a new approach — Agentic AI, which automates the entire pre-fabrication workflow from architecture specification to verified GDSII hand-off.
At the AI Infra Summit 2025, founder Shelly Henry shared how the company’s AI-driven platform, VerifAgent™, is transforming the economics and pace of chip design.
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5 Key Takeaways
Agentic AI for Chip Design: Moores Lab(AI) automates chip design workflows, reading specifications and producing verified design code.
From Spec to RTL: The platform translates design intent directly into Verilog or UVM code using large language models.
Three Work Modes: Engineers can work in Scratch, Edit, or Complete mode for new, modified, or legacy IP blocks.
Massive Productivity Gains: Early users report 92–97% time savings, reducing months of design work to hours.
Freedom from Vendor Lock-in: Teams can mix and match EDA tools easily, breaking the chains of traditional vendor dependency.
The Spark Behind Agentic AI
The story of Moores Lab(AI) began with one realization: chip design bottlenecks aren’t about automation—they’re about understanding.
“Before large language models, no system could read and comprehend a design specification,” says Henry. “Engineers had to translate every line into production-ready RTL. It was slow, tedious, and error-prone.”
Moores Lab(AI) changes that. Its agentic AI reads specifications just like a human, understands intent, and generates optimized Verilog or UVM code.
The system keeps refining its output until the design compiles cleanly.
The platform integrates seamlessly with industry-standard verification tools such as Synopsys VCS, Cadence Xcelium, and Siemens Questa, automatically fixing issues as it goes.
The company’s goal isn’t to replace EDA software but to remove the manual “glue work” that has long held back chip design productivity.
Middleware Meets Frontend Automation
Moores Lab(AI)’s platform works as a two-sided engine.
- On the backend, it acts as middleware connecting diverse EDA tools. It manages constraints, runs simulations, and coordinates toolchains — tasks that once required endless scripting.
- On the frontend, it writes Verilog, builds UVM testbenches, and optimizes power, performance, and area metrics.
The result is a hybrid system that serves as both an AI assistant and orchestration layer, dramatically reducing human effort without reducing control.
Designed for Real-World Engineering
In reality, no chip design starts from scratch. Some IP blocks are reused, others modified, and some built anew. Moores Lab(AI) reflects that reality with three intelligent working modes:
- Scratch Mode: For brand-new IP designs, where everything is generated from zero.
- Edit Mode: For modifying existing designs or adding features.
- Complete Mode: For integrating third-party or legacy IP unchanged.
Engineers simply declare the design status, and the AI automatically selects the optimal strategy.
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97% Productivity Gains: Tested and Proven
In early customer pilots, Moores Lab(AI)’s VerifAgent™ delivered performance leaps that once seemed impossible.
- Test plan creation: Reduced from 3 weeks to 10 minutes.
- Testbench generation: From 3 months to under 24 hours.
- Test case implementation: From 2–3 months to just one day.
These numbers translate to 92–97% productivity improvements and 7–10× faster design cycles.
At a time when chip design costs are soaring — with verification consuming up to 35% of project budgets — such efficiency gains are nothing short of revolutionary.
Current capabilities focus on digital design, with analog design automation expected in future releases.
Security at the Core
For semiconductor companies, intellectual property is sacred. Moores Lab(AI) was built with security and control as foundational principles.
All operations happen on-premises or within a customer’s private cloud. The AI models connect only through the customer’s own cloud subscription — whether Azure, OpenAI, Anthropic Claude, or Google Gemini.
EDA licenses remain customer-owned, and Moores Lab(AI) never accesses design data.
This architecture makes it a self-contained, enterprise-grade solution — giving companies the power of AI without the risk of data exposure.
Breaking the Chains of Vendor Lock-in
Historically, semiconductor companies have depended on single-vendor EDA ecosystems. The reason was simple: consistency, licensing convenience, and reduced operational risk.
But that uniformity came at a cost — limited flexibility and vendor dependency.
Moores Lab(AI) offers a way out. With a few configuration tweaks, teams can mix and match simulators, synthesizers, or P&R engines across projects.
What once required weeks of scripting and complex license setups is now plug-and-play.
This capability not only improves tool adoption and customization but also strengthens companies’ negotiating power when renewing EDA contracts.
Complementing, Not Competing
Unlike typical disruptors, Moores Lab(AI) isn’t looking to replace EDA giants like Synopsys, Cadence, or Siemens. Instead, it sits on top of existing EDA engines, automating the repetitive layers that connect them.
This complementary approach turns potential competitors into strategic partners, aligning AI-driven innovation with established industry workflows.
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The Bigger Picture: Toward Fully Automated Chip Design
Over the next three to five years, Moores Lab(AI) envisions agentic AI extending across RTL, verification, and backend design with increasing autonomy.
However, Henry stresses that human expertise remains irreplaceable. Architects will continue to make critical decisions, ensuring quality and intent in final designs.
Long term, the dream of fully automated semiconductor design may emerge — but always under human oversight.
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Why Chipmakers Are Paying Attention
Moores Lab(AI)’s combination of speed, flexibility, and security is winning attention from chipmakers eager to shorten design cycles, cut costs, and reclaim control over their workflows.
In an industry racing toward smaller nodes and complex SoC architectures, even a 10% efficiency gain is valuable. A 90% improvement? That’s transformative.
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Conclusion: Redefining the Semiconductor Workflow
Moores Lab(AI) isn’t just another AI startup. It’s redefining the workflow fabric of semiconductor design — bridging EDA tools, automating verification, and empowering engineers to focus on creativity rather than coding.
For chip companies struggling with shrinking timelines and ballooning verification costs, Agentic AI could be the next inflection point — as pivotal as the move from manual layout to RTL itself.
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