The chip design VLSI course includes different types of processing steps to finish the entire flow. Anyone, who just started his career in the VLSI industry has to understand all the steps of the VLSI design flow. Every step of the VLSI design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly. Let us explore an NPTEL course by Prof. Sneh Saurabh, IIIT Dehli that teaches the RTL2GDS flow in great detail.
Who is Sneh Saurabh ?
Prof. Sneh Saurabh obtained his Ph.D. from IIT Delhi in 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000.
He has rich experience in the semiconductor industry, having spent 16 years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation.
Dr. Saurabh has been involved in developing some of the well-established industry-standard EDA tools for clock synchronization, constraints management, STA, formal verification, and physical design. He has been teaching semiconductor-specific courses since 2016 at IIIT Delhi.
What is RTL to GDS- VLSI Course?
Whenever we design an Application Specific Integrated circuit (AISC) we follow a sequence of steps. These steps start from an RTL file and end at a GDS file. In between, there are various steps involved. The prominent ones include Logic Synthesis, Physical design, Verification and testing.
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Why this VLSI course is special?
I found this course different from other courses on the internet because not only does it teach how the design flow goes but it makes us practice the concepts using open-source tools.
VLSI design is a highly practical field involving design tools at almost every step and Prof. Sneh Saurabh has shared his vast industry experience in his course.
Apart from engrossing theoretical tutorials, this course has lab tutorials in open-source tools. For example, physical design involves an array of complex steps like floorplanning, placements, CTS, and routing. These topics as they may sound are practical by nature.
There are certain sets of rules you need to follow for floor planning and routing like macro placement guidelines, dealing with voltage drop hotpots, and congestion in routing. Without the involvement of EDA tools, it’s nearly impossible to understand these concepts.
Industry-level tools like Cadence Design Suite and Synopsys Primetime require a Linux environment and come with licensing issues. Sneh sir acknowledged this issue and through his PhD Scholars, he ensured that learners gain practical experience with open-source tools.
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There are tutorials at the end of each week’s lectures. There is:
- Introduction to TCL
- High-level synthesis using Bamboo
- Simulation-based verification using Incarus
- Logic synthesis & optimization using Yosys
- Static timing analysis and Power analysis using OpenSTA
- Chip-planning, placement, CTS & routing using OpenRoad
Another striking feature of this course is that Prof. Sneh explains each step not only for the sake of concept but also for how the EDA tool perceives each design step.
Let us take an example through the personal experience of a course learner.
Doing Static timing analysis requires performing setup and hold checks i.e. late analysis and early analysis. We have formulas for setup time and hold time to do calculations manually.
This is for the sake of us to understand and do calculations but how does the tool do STA?
Well, timing graphs are the answer. Tools like OpenSTA and Primetime make a timing graph out of the netlist and then backtrack it to calculate signal latency.
Prof. Saurabh explains this in great detail in his RTL2GDS course. This benefits not only VLSI design engineers but also software engineers who work on the development of major EDA tools like Cadence, Siemens EDA, and Synopsys.
Prof. Saurabh teaches the concept of Reduced binary decision diagrams (greatly reduces the compile time for doing STA) which can be a great insight for software developers in the EDA industry.
Why should you consider doing this course?
Most of the VLSI design flow courses available on the internet come at high costs (Rs. 20k-32k). This free NPTEL course explains the ASIC design flow in great detail in a way that caters to hardware as well as software engineers. The open-source tools taught in the course pose an added advantage.
The course can be best complemented by the book Introduction to VLSI Design Flow by Prof. Sneh Saurabh himself.
Watch the course here
Lecture notes can be accessed from here
Summing up
India currently is in dire need of good VLSI engineers. The first make-in-India chips will be out by December 2024 and once the first lineup is out the revolution will begin. This revolution would need the fuel of talent and hard work of Millenials and the GenZ.
India’s biggest strength i.e. youth population must be trained for the task ahead and Professors like Sneh Saurabh and his NPTEL course are the best way to do that. Thanks to NPTEL for training the youth at large. Here’s to the greater good.
The article is written by Himanshu Singh, UG at NIT Jamshedpur.
