NAND’s Next Leap: SK Hynix Targets 400 Layers by 2025

Samsung recently commenced mass production of 290-layer V-NAND and has set a goal of surpassing 1000 layers by 2030.

Introduction

SK hynix is advancing in the NAND flash memory sector by developing a groundbreaking 400-layer NAND chip, aiming to start mass production by late 2025.

This ambitious project involves close collaboration with supply chain partners to innovate the required process technologies and equipment for producing 400-layer and higher NAND chips.

This information is based on a recent article by the Korean media outlet ETNews, citing industry sources.

Industry-Leading Target: SK Hynix’s 400-layer target positions them as a leader in NAND technology.

Hybrid Bonding Technology: The company plans to use hybrid bonding to achieve this milestone, which involves combining different wafer layers.

Supply Chain Collaboration: SK Hynix is working closely with partners to develop the necessary technology and equipment for 400-layer NAND.

Potential Benefits: Achieving this goal could lead to higher capacity, faster storage devices, and potentially lower costs for consumers.

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Understanding 400-Layer NAND

NAND flash memory is essentially a type of non-volatile storage that stores data in cells arranged in layers. Think of it like a stack of pancakes, where each pancake represents a layer.

A 400-layer NAND simply means that there are 400 layers of these storage cells stacked on top of each other within a single NAND chip.

Why is this significant?

Increased Storage Density: More layers mean more storage capacity in the same physical space. This is crucial for devices like smartphones and laptops where size is a premium.

Improved Performance: While the primary benefit is increased density, advancements in NAND technology often lead to performance improvements as well, such as faster read and write speeds.

Potential Cost Reduction: As production scales up, the cost per gigabyte of storage tends to decrease. This could lead to more affordable storage solutions for consumers.

    To summarize, 400-layer NAND represents a significant leap in storage technology, promising to deliver higher capacities, better performance, and potentially lower costs. It’s a testament to the ongoing innovation in the semiconductor industry.

    Advancing NAND Technology with Hybrid Bonding

    To achieve this feat, SK hynix plans to use hybrid bonding technology, which is anticipated to introduce new packaging materials and components suppliers into the supply chain.

    Hybrid bonding involves new bonding materials and various technologies for connecting different wafers, including polishing, etching, deposition, and wiring.

    SK Hynix aims to have the necessary technology and infrastructure ready by the end of next year.

    Industry Trends in NAND Chip Layering

    The push to increase the number of layers in NAND chips is not unique to SK hynix. Other semiconductor manufacturers are also striving for higher layer counts:

    • Samsung recently commenced mass production of 290-layer V-NAND and has set a goal of surpassing 1000 layers by 2030.
    • Micron introduced a product featuring 276-layer 3D NAND in July.
    • Kioxia achieved 218 layers in 2023 and suggests that 1000 layers may be possible by 2027.

    In comparison, SK hynix showcased a 321-layer NAND sample in August 2023. To achieve the 400-layer milestone, the company plans to implement hybrid bonding with a “wafer-to-wafer” (W2W) structure.

    This approach is different from their current “Peripheral Under Cell” (PUC) method, which stacks cells on top of the peripheral driving circuit area.

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    Addressing Layering Challenges

    The transition to hybrid bonding aims to solve challenges with increasing the number of layers.

    High heat and pressure can damage peripheral components during cell stacking. SK hynix plans to manufacture cells and peripheral circuits on separate wafers.

    They will bond these wafers later. This method allows stable layer increases while protecting peripheral components.

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    SK hynix’s Strategic Development

    The shift to hybrid bonding is strategic for SK hynix. It aims to maintain a competitive edge in the NAND flash memory market.

    The company is exploring new bonding materials. Advanced technologies are being leveraged. SK hynix wants their 400-layer NAND chips to be high-performing and reliable.

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    Future Prospects

    When asked by ETNews about the 400-layer NAND development, SK hynix declined to provide specific details regarding the technology development or mass production timelines.

    However, the company is clearly focused on overcoming the technological hurdles and aligning its production capabilities to meet the market demand for higher capacity and more efficient NAND flash memory.

    Implications for the Semiconductor Industry

    The development of 400-layer NAND flash memory by SK hynix and similar advancements by other leading manufacturers signify a major leap in semiconductor technology.

    These advancements are expected to drive significant improvements in data storage capabilities, performance, and efficiency. As the industry progresses towards 1000-layer NAND chips, the innovations in manufacturing processes and material sciences will likely lead to broader applications and new possibilities in data storage solutions.

    Conclusion

    SK hynix’s target of producing 400-layer NAND flash memory by 2025 marks a significant step forward in the semiconductor industry.

    By leveraging hybrid bonding technology and collaborating with supply chain partners, the company aims to set new benchmarks in NAND chip production.

    As the race to higher layer counts intensifies, SK Hynix’s advancements will play a crucial role in shaping the future of data storage technology.

    Kumar Priyadarshi
    Kumar Priyadarshi

    Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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