Introduction
The semiconductor industry stands at a pivotal crossroads. For years, ASML’s extreme ultraviolet (EUV) lithography machines—especially the cutting-edge High-NA EUV scanners—have been hailed as the heart of next-generation chip manufacturing. But a new trend is emerging. Leading chipmakers like Intel, TSMC, and Samsung are reportedly shifting focus from lithography to advanced etching technology as transistor designs evolve.
This shift could reshape the future of advanced chipmaking, impacting global supply chains, technology investments, and competitive dynamics.
Here’s a closer look at why ASML’s High-NA EUV might be losing its shine.
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5 Key Points at a Glance
Intel insiders say future chips will rely more on etching than lithography due to new transistor architectures.
Next-gen designs like GAAFET and CFET reduce lithography dependency by focusing on lateral precision.
TSMC and Samsung delay adoption of High-NA EUV, citing cost and architectural shifts.
Chinese companies like AMEC accelerate plasma etching innovations, supporting advanced nodes without EUV.
This trend could reshape semiconductor manufacturing and slow High-NA EUV’s market dominance.
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Background: Lithography’s Role in Chipmaking
Lithography prints circuit patterns onto silicon wafers, enabling billions of transistors to function.
ASML’s EUV machines, particularly the High-NA (numerical aperture) EUV systems, promised finer patterning and better chip density.
But lithography is just one step. After patterning, etching removes unwanted material to define transistor structures, while deposition layers materials to build the chip.
Currently, most chips use FinFET architecture, where the transistor’s gate wraps around three sides of the channel.
But as chips shrink beyond 3nm, manufacturers turn to Gate-All-Around FETs (GAAFET) and Complementary FETs (CFET). These designs wrap the gate entirely around the channel or stack transistors vertically, requiring ultra-precise lateral etching.
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Intel Director: Etching Gains Prominence Over Lithography
According to a recent report on investment platform Tegus, cited by Wccftech and Tech Fund, an unnamed Intel director revealed a strategic pivot.
They stated that etching technology will become more critical than lithography in shaping future transistor features.
This insight reflects how GAAFET and CFET designs demand precision material removal, which only advanced etching techniques can deliver.
As a result, chipmakers may reduce reliance on costly and complex lithography tools like High-NA EUV scanners.
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TSMC and Samsung Delay High-NA EUV Adoption
TSMC Senior Vice President Kevin Zhang confirmed at the NA Technology Symposium that the company would skip High-NA EUV for its A14 process node and continue with existing 0.33-NA EUV scanners.
TSMC plans to adopt High-NA EUV later, around its A14P node, but no definitive timeline exists.
Samsung, too, reportedly postpones integrating High-NA EUV into its DRAM production. The company cites the high cost of High-NA EUV tools and architectural changes in DRAM as reasons for the delay.
China’s Etching Push Challenges EUV Monopoly
With U.S. export restrictions limiting China’s access to EUV tools, local firms have doubled down on etching innovation.
Chinese semiconductor companies like Naura Technology, SiCarrier, and AMEC have made remarkable progress. AMEC’s plasma etching business reportedly grew at a 50% compound annual growth rate (CAGR), according to Science and Technology Innovation Express News.
AMEC Chairman Gerald Yin confirmed that 5nm production can be achieved using DUV lithography combined with advanced etching, bypassing EUV entirely. Rumors circulate that Huawei and SMIC have already made breakthroughs at 5nm nodes without EUV.
Lithography vs Etching in Advanced Nodes
| Aspect | Lithography (EUV) | Etching |
|---|---|---|
| Role | Initial patterning | Precise material removal |
| Cost | Very high (High-NA EUV ~$200M+) | Moderate to high, but improving |
| Impact on Transistor | Defines pattern dimensions | Shapes final transistor profile |
| Adoption Challenges | Tool complexity, cost, export limits | Technology maturity, precision control |
| Future Relevance | Potentially reduced in GAAFET/CFET era | Increasingly critical |
What This Means for the Semiconductor Industry
This evolving landscape highlights a potential realignment of manufacturing priorities. While ASML’s High-NA EUV remains a marvel of engineering, its high cost and complexity may limit widespread adoption.
At the same time, etching technology offers a more cost-effective route to meet the demands of emerging transistor architectures. This could democratize advanced chip production, especially for Chinese firms constrained by geopolitical factors.
Intel’s insider view signals that future innovation may hinge less on lithography breakthroughs and more on mastering etching precision.
Conclusion
ASML’s High-NA EUV lithography faces significant challenges as chipmakers explore new architectures that demand advanced etching.
The delays by TSMC and Samsung, coupled with China’s rapid progress in plasma etching, hint at a more balanced future where etching and lithography share the spotlight.
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