TSMC’s CoWoS Technology to Revolutionize AI and HPC by 2027

TSMC's latest CoWoS packaging technology aims to revolutionize AI and HPC processors.

Introduction

TSMC ‘s unveiled plans for its next-generation CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. Announced at the Open Innovation Platform (OIP) Ecosystem Forum in Europe, the new design will feature a massive 9x reticle size by 2027.

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This innovation will enable integration of twelve HBM4 memory stacks, transforming AI and high-performance computing (HPC) capabilities.

This breakthrough highlights TSMC’s commitment to advancing semiconductor technology, setting new performance standards for future processors.

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Key Highlights

  1. 9x Reticle Size: Offering 7,722 square mm of space for chip integration.
  2. Enhanced Performance: Supports twelve HBM4 memory stacks, ideal for AI and HPC applications.
  3. Vertical Stacking: Combines 1.6nm chips with 2nm chips to increase transistor density.
  4. Cooling Challenges: Liquid cooling becomes crucial for managing high power usage.
  5. Future Launch: 5.5x reticle package coming by 2025; 9x version by 2027.

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What is CoWoS?

CoWoS is a cutting-edge chip packaging technology introduced by TSMC in 2016. It allows for stacking chips like memory and logic in a single package, boosting data transfer speeds and reducing latency.

Initially, CoWoS packages had a 1.5x reticle size. Today, they have evolved to 3.3x reticle sizes, supporting eight HBM3 stacks.

The upcoming 9x reticle CoWoS package will significantly expand these capabilities, meeting the rising demand for powerful AI and HPC chips.

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9x Reticle Size: A Game-Changer

The planned 9x reticle CoWoS technology will provide unprecedented scalability. With 7,722 square mm of packaging area, it will accommodate up to twelve HBM4 stacks. This design will cater to data-heavy AI models and HPC systems that demand maximum performance and efficiency.

High-end AI processors leveraging this package will debut between 2027 and 2028, as reported by industry sources.

Vertical Stacking for Enhanced Power

TSMC plans to use System on Integrated Chips (SoIC) stacking to combine different process nodes. For example, the 9x reticle package will stack 1.6nm chips on 2nm chips. This increases transistor density, boosting overall chip performance and efficiency.

Such advancements will play a crucial role in powering AI-driven technologies like deep learning, autonomous vehicles, and big data analytics.

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Challenges in Size and Cooling

Scaling CoWoS packages to larger sizes introduces challenges. The 5.5x reticle package, set for release in 2025, will require a substrate of 100x100mm. The 9x reticle version will need substrates exceeding 120x120mm.

Larger substrates pose design challenges, particularly for data centers. These systems will also consume significant power, potentially reaching hundreds of kilowatts per rack. Effective cooling methods, like liquid and immersion cooling, will be essential to handle this heat.

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Roadmap to Innovation

TSMC’s roadmap includes a 5.5x reticle package launch by 2025. This version will support twelve HBM4 stacks, serving as a stepping stone to the 9x reticle package in 2027.

These advancements align with TSMC’s goal to stay ahead in the semiconductor race. By meeting customer demands for higher performance, the company continues to lead the industry.

Impact on the Semiconductor Industry

TSMC’s CoWoS advancements will have widespread effects. AI and HPC systems, critical for industries like healthcare, finance, and automation, will benefit immensely.

The larger packages will enable faster, more efficient processors, accelerating innovation.

Rival chipmakers may also intensify their efforts, pushing the boundaries of semiconductor packaging further. Additionally, liquid cooling technologies will become standard as processors demand higher power and heat management.

Conclusion

TSMC’s 9x reticle CoWoS technology represents a major leap for AI and HPC. By 2027, this innovation will redefine chip performance, enabling faster and more efficient systems.

As TSMC overcomes challenges like heat dissipation and large substrates, it cements its role as a pioneer in semiconductor technology.

With the rise of AI-driven applications, the company’s advancements will power the next wave of global technological progress.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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