July 28th marks a significant day for VLSI jobs professionals seeking new career opportunities. With an array of job openings in the VLSI domain, this date presents a promising gateway for those aspiring to excel in the field of Very Large Scale Integration. Explore the latest job listings and embark on a path of professional growth
- ???????????????????????? ???????????????????????????????? ???????????????????????????? ???????????????????????????? Is Hiring ???????????????? ???????????????????????????????? ???????????????????????? ???????????????????????????????????? For ???????????????????? Location!!!
???????????????????????????????????????? : 10+????????????????????
Interested share resume or references to [email protected]
???????????????????????? ???????????????????????????????? :
– Experience in Physical and WLM ???????????????????????????????????? (???????????????????????? ????????????????????????????????).
– ????????????????????: Design compiler/???????????????????????? ????????????????????????????????, DFT Compiler, Primetime, Innovous, Virtuoso, etc.
– Experience in Chip Level and Block Level Design Implementation.
– Experience Timing and Design Signoff (Primetime).
2. Cientra is hiring 7-15Yrs Sr RTL Design _FPGA Design engineer
FPGA lead is responsible for providing in house FPGA solutions to bring up various IPs at Cientra Tech Solutions as a Solution provider.
Understanding design requirements for FPGA implementation
Participate in the architecture finalization of the FPGA solution Perform pin selection working with board design team
l Understand clocking at board level and identify internal to FPGA clocking strategies
Design and implement complex functions required to complete the solution
Generate IPs/Macros from FPGA vendor/tool for integration, understand the requirements and available IPs and suggest modifications to be able to map to FPGA resources
Created RTL for glue logic and support functions, integrate IPs or blocks to build the FPGA core, take design through RTL checks
Create and release tags for verification and synthesis Create FPGA synthesis and Timing closure for the project and create FPGA images for lab validation.
· Development in Matlab / Simulink-based experience, object-oriented MATLAB programming
l Should have good understanding of how to implement “ready to use” FPGA IPs like high speed PHYs, DDR Controller, ARM CPUs etc
Follow us on Linkedin for everything around Semiconductors & AI
Have you Experienced in #pcie?
Greetings from Cientra (An ISO 9001:2015 Company) Tech solutions!!
looking for professionals with PCIe experience in #verification, #bangalorelocation
Exp required: #4+yrs
If you wish to know more about these positions or requirements, please share your updated resumes to [email protected] or DM me directly in Linked-In
l Good knowledge on how SW interaction works or Linux boot on Xilinx is a plus.
4. Niksperri Technologies Pvt Ltd!!!
We are Hiring for Standard cell CHAR & Design Engineers
Experience: 2 – 8 years
Notice Period: Immediate to 30 Days
Location: Bangalore
If interested, please share your updated resume to
[email protected] or call 9535906140
Please find the JD for Standard cells CHAR & Design below.
• Strong understanding of Custom Digital circuits & optimization for better PPA.
• Hands-on experience running SPICE simulations. Parasitic extraction and circuit optimization for power/performance/robustness/density.
• library design, characterization, NLDM, CCS modelling
• knowledge of all the collateral views & about their generation (gds2, .lib, .v, IBS, .db,…)
• CMOS and FinFet device characteristics and design rules.
• characterization & modeling (.lib generation). Library characterization for timing, noise, power and variation models (non-linear delay models & composite current source models, parametric on chip variation models)
• Working on Good experience of EDA tools like Cadence Spectre, Virtuoso, waveform viewer, 45nm/28nm & 16nm/7nm technology node
• Experience in scripting languages like Linux, Perl, Python, etc. and their environments
Good communication and analytical skills. Quick learner with debugging skills.
5. INSEMI has DFT OPENING FOR JUNIOR ENGINEER, with 0-1 year experience
Job ID : IN1196
Title : Trainee DFT Engineer
Job Description :
VerilogDigital CMOS
Forward your resume to [email protected] with subject JOBID_NAME_COLLEGE YEAR.
6.
INSEMI has openings for
1)Job ID : IN1194
Job Title : SWR300 Firmware Testing
Designation: Test Engineer/SoftwareEngineer
Job Description :
Minimum of B.E./ B.Tech. with 2 – 6 years’ experience in firmware/BIOS testing
understanding of x86/ARM architecture
understanding of PC hardware blocks
knowledge of testing fundamentals
Good oral and written communication skills
Working knowledge of Linux and Windows OS
Excellent attitude towards work
Experience with any of scripting languages (e.g. Perl, Python)
For referal forward your resume to [email protected] with subject as JOBID_NAME_Experience.
