What are 4 Major Issues with EUV: IBM at IEDM 2023

IBM's update highlighted a significant reduction of over 50% in the depth of focus for High-NA EUV. This reduction necessitates precise control over resist thickness and planarity, requiring them to be maintained below 30 nm.

Introduction

The International Electron Devices Meeting (IEDM) 2023 witnessed a groundbreaking state-of-the-art update from IBM, shedding light on the latest advancements in Extreme Ultraviolet (EUV) lithography.

As the semiconductor industry continues to push the boundaries of Moore’s Law, EUV technology plays a pivotal role in enabling the production of smaller and more powerful chips.

In this blog post, we will delve into key revelations made by IBM, emphasizing the challenges and innovations in single-exposure EUV, dose requirements, and the impact of High-NA EUV on chip manufacturing.

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What is EUV and Why it matters?

Extreme Ultraviolet Lithography (EUV) is a cutting-edge technology used in semiconductor manufacturing to create smaller and more powerful microchips. Traditional lithography techniques use ultraviolet light with wavelengths around 193 nm, but as the industry strives to produce smaller transistors and increase chip density, the limitations of these wavelengths become apparent. EUV lithography addresses this challenge by utilizing extreme ultraviolet light with wavelengths in the range of 13.5 nm.

Here’s why EUV matters in the context of semiconductor manufacturing:

Smaller Features and Increased Density:

  • EUV enables the production of smaller features on semiconductor wafers. As the wavelength of EUV light is significantly shorter than that of traditional lithography, it allows for more precise patterning and smaller feature sizes. This, in turn, contributes to the increased density of transistors on a chip.

Moore’s Law and Continued Scaling:

  • Moore’s Law, a principle formulated by Gordon Moore, co-founder of Intel, predicts that the number of transistors on a microchip will double approximately every two years, leading to increased performance and capabilities. EUV lithography is crucial in continuing the trend of miniaturization and scaling down semiconductor devices.

Improved Resolution and Precision:

  • The shorter wavelength of EUV light enables higher resolution and precision in the lithographic process. This is particularly important as semiconductor manufacturers strive to produce chips with features in the single-digit nanometer range.

Reduced Complexity and Multi-Patterning:

  • EUV lithography simplifies the manufacturing process compared to the multi-patterning techniques used with traditional lithography at higher wavelengths. Multi-patterning involves multiple exposures to achieve the desired feature sizes, making the process more complex and time-consuming.

Enhanced Yield and Cost Efficiency:

  • EUV lithography can contribute to higher yields in semiconductor manufacturing. By simplifying the process and reducing the number of steps required for patterning, EUV can improve the cost efficiency of chip production.

Future-Proofing Technology:

  • As semiconductor technology advances, the demand for smaller and more efficient chips continues to grow. EUV lithography is a key enabler for future semiconductor nodes, ensuring that the industry can keep up with the increasing demands for performance, energy efficiency, and functionality in a wide range of electronic devices.

Read More: What are 3 Major challenges in EUV Lithography ?

EUV has the burden to carry moore’s law ahead.

1. Pitch Limits and Stochastic Challenges in Single-Exposure EUV

One of the critical insights shared by IBM pertains to the pitch limits of single-exposure EUV, which currently stand at over 28 nm. These limits are attributed to stochastic effects, a phenomenon that introduces variability in the manufacturing process. Stochastics pose challenges in achieving the desired resolution for smaller features, necessitating a reevaluation of existing lithography techniques.

IBM’s acknowledgment of this limitation underscores the industry’s ongoing quest for solutions to overcome stochastic effects. Researchers and engineers are actively exploring novel approaches and materials to mitigate these challenges and unlock the full potential of single-exposure EUV lithography.

Researchers are exploring advanced chemical amplification resists (CARs) and new materials to enhance the sensitivity of single-exposure EUV lithography, mitigating stochastic effects. Additionally, process optimization, innovative mask designs, directed self-assembly (DSA), and the application of machine learning are being pursued to collectively overcome challenges and unlock the full potential of this critical semiconductor manufacturing technology.

Read More: What are 3 Major challenges in EUV Lithography ?

2. EUV Dose Requirements: A Balancing Act

EUV doses (The specified doses indicate the energy required to expose the resist and define the features on the semiconductor wafer) play a crucial role in determining the success of lithographic processes.

IBM’s update revealed that for wider features, EUV doses are set at a minimum of 80 mJ/cm2, with even higher doses of up to 100 mJ/cm2 required for smaller features. Additionally, cuts and blocks demand doses around 40 mJ/cm2.

EUV lithography aims not only for high resolution but also for efficient throughput in chip manufacturing. Balance between achieving the desired feature sizes and maintaining a practical production speed is essential for cost-effective and timely semiconductor fabrication.

Controlling and maintaining consistent EUV doses across the entire wafer surface is crucial for ensuring uniformity in the lithographic process. Variations in dose levels can lead to defects, inconsistencies, and reduced yields in semiconductor manufacturing.

Read More: Canon Lithography Tool price will have one digit less than ASML EUVs: CEO

3. High-NA EUV Depth of Focus Reduction: Navigating Thin Resist Layers

High Numerical Aperture (NA) EUV lithography offers enhanced resolution, but it comes with a trade-off.

IBM’s update highlighted a significant reduction of over 50% in the depth of focus for High-NA EUV. This reduction necessitates precise control over resist thickness and planarity, requiring them to be maintained below 30 nm.

The reduced depth of focus makes High-NA EUV more sensitive to variations in resist thickness and planarity. Maintaining precise control becomes paramount, as deviations beyond 30 nm can lead to focus errors and decreased pattern fidelity.

Additionally, Semiconductor devices are increasingly adopting 3D structures for improved performance and density. The reduced depth of focus poses challenges in maintaining uniformity and precision in the formation of vertical structures.

The increased complexity may lead to challenges in process scalability and reproducibility.

4. Field Stitching and Chiplet Decomposition for High-NA EUV

To overcome the challenges associated with High-NA EUV, IBM proposes the adoption of field stitching or chiplet decomposition for high-performance chips. This approach acknowledges the limitations in achieving a seamless manufacturing process for large, high-performance chips using traditional methods.

Field stitching involves the combination of smaller exposed fields to create a larger pattern, allowing for more manageable lithography processes.

Chiplet decomposition, on the other hand, involves breaking down a large chip into smaller, independent chiplets that can be individually manufactured and later integrated.

Chiplet adoption

Conclusion

IBM’s state-of-EUV update at IEDM 2023 provides valuable insights into the current challenges and future directions of EUV lithography.

Navigating stochastic effects, dose optimization, and High-NA EUV challenges, researchers and engineers remain committed to pushing innovation boundaries.
Proposed solutions like field stitching and chiplet decomposition underscore the industry’s dedication to advancing semiconductor technology for the next era of performance and miniaturization.

Reference: Fred Chan on X

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