Introduction
As designs shrink to 7/5nm and beyond, quantum effects are emerging as a more widespread and significant problem, and one that ultimately will affect everyone working at those nodes.
Scientists have observed, studied, and theorized quantum effects for years, extending beyond the semiconductor industry. For instance, researchers have documented quantum tunneling, where particles such as electrons defy classical expectations by passing through energy barriers they traditionally couldn’t overcome, in alpha particle decay research for nearly a century.But in the chip world, these quantum effects show up in a variety of strange behaviors that are becoming increasingly problematic.
- Increased Tunneling Leakage: At these small scales, electrons can tunnel through insulating layers, causing unwanted current flow and increased power consumption.
- Enhanced Gate Variability: The quantum nature of electrons makes their behavior less predictable, leading to variations in how transistors turn on and off. This variability can affect chip performance and reliability.
- Significant Power Density Limitations: Packing more transistors into a smaller space increases heat generation. Quantum effects can worsen this by limiting how efficiently heat can dissipate, potentially leading to thermal runaway.
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Rise of quantum effects
“Quantum effects happen in the device as soon as certain device dimensions become very small, due to scaling and its associated requirements,” said Anda Mocuta, director of technology solutions and enablement at Imec.
As a consequence of gate dielectric scaling and that of the increasing electric fields within the device, the carriers in the inversion layer (check below) are no longer located at the silicon dioxide-silicon interface, but somewhere below, resulting in an increased effective dielectric thickness.This effect has existed in CMOS technologies for a while now, and it is a quantum effect.
“Quantum effects have always been there,” said David Fried, vice president of computational products at Coventor, a Lam Research Company. To truly understand transistors, we need to grasp how atoms arrange themselves in patterns and how quantum mechanics influences their behavior.
Quantum tunneling
Quantum tunneling in transistors refers to the phenomenon where electrons can pass through energy barriers that would be classically impossible to overcome.
In classical physics, electrons would need to possess sufficient energy to surmount the potential barrier formed by the energy difference between the source and drain terminals. However, in quantum mechanics, electrons have wave-like properties and can exhibit tunneling behavior. This means that electrons have a probability of passing through the barrier even when they do not have enough energy to overcome it classically.
Fig – Schematic of electron wavefunction showing tunneling through thick vs. thin barrier
Quantum tunneling occurs due to the wave nature of electrons, as described by the Schrödinger equation. This makes transistors difficult to control and often increases power consumption due to greater leakage current.
Volume inversion
In a transistor, the term “inversion” refers to the creation of a layer of charge carriers that is opposite to the type of carriers in the bulk material of the transistor. This inversion layer forms a conductive channel between the source and the drain, allowing current to flow through the transistor.
Surface Inversion: In conventional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the inversion occurs at the surface of the semiconductor, right underneath the gate oxide. When a voltage is applied to the gate, it creates an electric field that attracts charge carriers (electrons for n-type, holes for p-type) to the surface, forming an inversion layer. This layer is very thin and essentially two-dimensional.
Volume inversion: When transistors are scaled below 7nm, the transistor body volume becomes so small that inversion does not confine to a layer but extends to the entire body. All of a sudden, the device becomes fully depleted instead of having surface inversion.
The cause of volume inversion is primarily due to the aggressive scaling of transistor dimensions. As the body thickness of the transistor decreases, the inversion layers from the top and bottom surfaces start to overlap, leading to volume inversion.
Quantum confinement
Quantum confinement refers to the phenomenon where the motion of electrons in a material is restricted to a very small space. Transistor dimensions are so small that they approach the wavelength of the charge carriers (electrons/holes).
Quantum confinement can manifest in the channel region where the electrons flow. It causes an inversion layer in the channel to be slightly away from the Si/SO2 interface. This increases the gate oxide thickness and hence brings variations in threshold voltages.
As gate length is reduced there are very few scattering centers between source and drain. As the fin widths (channel in FinFets) scale further below 7nm and gate lengths below 20nm, quantum confinement and ballistic transport of carriers will become more pronounced.
This can improve the performance of transistors, leading to faster operation, lower power consumption, and higher integration density. Leakage current occurs when charge carriers tunnel from the source to the drain, even when the transistor is meant to be off, posing a disadvantage for Micro LED technology.
Observing quantum effects
With every technology development, it takes years from the time the first person begins working on 7nm until it moves into high-volume manufacturing. Over those years, you’re running into some effect and you’re asking, ‘What is happening here?’ You start to dig in and you realize it’s this effect and that effect. Over those years, you’re running into these interrelated things that you didn’t think were coming or didn’t know they would be there, and then you pull it apart and address it.”
Remedies for quantum effects
“Some aspects we understand well and can deal with, such as threshold voltage adjustments to account for threshold voltage shifts,” said Imec’s Mocuta. “Most aspects we can model and understand well, and we can tweak parameters to mitigate partially. Some aspects may remain fundamental.”
High k & Metal Gate for Mature nodes
At 130/90/65nm polysilicon depletion effect became a measurable. This effect occurs due to the presence of a polysilicon gate electrode on top of the silicon dioxide insulating layer.
Scientists went off and studied, learned it, and built it into their predictive device models. Then they proposed things like high-k & metal gate. Metal gate got rid of the poly silicon gate and the dielectric material between the gate and channel was chosen of high dielectric strength (k).
Fig – Metal gate improvement over polysilicon gate
As the dielectric strength of a material increases, a greater number of electric field lines pass through it, improving the electric field interaction within the channel. This increased field strength provided more efficient control over the flow of carriers. A high K dielectric also increases the gate capacitance and thus has a doubling effect on charge carrier control.
Gate tunneling was a key reason for the introduction of high-dielectric-constant gate materials (eg Aluminium, Titanium dioxide). Their increased physical thickness for a desired equivalent oxide thickness reduces tunnelling. But at advanced nodes, that isn’t possible because gate oxides shrink with the rest of the features.
Move towards GAA transistors
Quantum effects become more pronounced at advanced notes like 7/5nm. The transistor body is so small that the benefits of increasing gate oxide thickness get nullified by the small size of the gate.
As fins (channels in FinFets) get thinner, there is very little surface area for the gate electrode to control the flow of carriers. This ultimately will force us to move towards gate-all-around transistor structures using nanowires or nanosheets.
Fig – GAA nanowire transistor
In GAA transistors, the gate electrode surrounds the channel region, forming a cylindrical or rectangular structure. This design ensures that the gate has direct influence over the entire channel, providing better electrostatic control compared to transistors where the gate is located only on one side of the channel.
Conclusion
These were some of the solutions for tackling ‘known’ quantum effects. In the coming years, as the production of advanced notes increases, we will face more effects to deal with, requiring much more engineering throughout the supply chain.
With TSMCs going towards the N2 tech node and intel’s 18A on the other hand, fabrication units will dig much deeper into the intersection of electrical engineering and quantum physics. Quantum effects shall be considered more of a new thing than a set of critical design criteria. The question is whether this ultimately will lead to technological advances that can solve these effects?
