What are Top EDA Tools Certified by TSMC for Nodes Upto 2 nm

This Certification assures chip designers that these tools will work properly with TSMC's cutting-edge manufacturing and allows them to leverage the full potential of the new processes.

Introduction

With the announcement of its 2-nanometer (nm) process technology and aspirations for even smaller 1.6 nm chips on the horizon, the semiconductor industry braces for a new era of innovation. But behind every groundbreaking semiconductor chip lies a sophisticated design process, powered by Electronic Design Automation (EDA) tools. Recognizing the critical role of EDA tools in driving innovation, TSMC has partnered with industry-leading EDA companies like Cadence, Synopsys, and Siemens to optimize their EDA suites for its latest process nodes.

Why Certification?

TSMC has a program to certify EDA tools that are compatible with their latest and most advanced manufacturing processes. This is important because these new processes, like 2 nanometer (nm) technology, allow for cramming more transistors onto a chip, which can make them faster and more efficient. But to take advantage of these processes, engineers need EDA tools that can handle the complexities involved.

By certifying a “host of top EDA tools,” TSMC is essentially giving the thumbs up to certain software programs from companies like Cadence, Siemens, and Synopsys. This assures chip designers that these tools will work properly with TSMC’s cutting-edge manufacturing and allows them to leverage the full potential of the new processes.

This collaboration between TSMC and EDA toolmakers is crucial for the continued development of ever-smaller and more powerful chips.

This compatibility is crucial for several reasons:

  • Functionality: EDA tools need to understand the specific characteristics of TSMC’s processes to generate accurate results during chip design and simulation.
  • Yield: Ensuring the tools work correctly helps reduce errors and improves the yield, which is the percentage of chips that function properly after manufacturing.
  • Time-to-Market: Using certified tools avoids compatibility issues that could slow down the design process and delay bringing products to market.

By having a pool of certified tools, TSMC gives chip designers confidence that these tools will work seamlessly with their manufacturing, allowing them to focus on designing high-performance chips.

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Cadence: Pioneering 3D ICs, Advanced Nodes, and Photonics

Image Credits: Cadence

Cadence and TSMC have recently joined forces to enhance Cadence’s suite of tools for TSMC’s cutting-edge 2-nanometer process technologies. This collaboration spans various applications, including digital and analog design flows, as well as semiconductor power integrity analysis.

Notably, Cadence’s Innovus Implementation System and Genus Synthesis Solution are now officially certified for TSMC’s N2 design flows. Additionally, the Cadence Integrity 3D-IC platform has been bolstered with improved capabilities to tackle intricate multi-chip designs using TSMC’s 3DFabric technologies.

Furthermore, the partnership encompasses the optimization of custom or analog tools for TSMC’s N2 Process Design Kit (PDK). This optimization extends to platforms like the Virtuoso Schematic Editor and the Virtuoso ADE Suite, which facilitate advanced circuit simulation and optimization crucial for high-performance and low-power semiconductor applications.

The collaboration seeks to advance photonic integrated circuit design and introduce new workflows for TSMC’s COUPE technology. They’ve launched a range of IP cores for TSMC’s N3 process technology. These cores support various interfaces, including UCIe, DDR5, LPDDR5, GDDR6, PCIe 5.0/CXL2.0, and PCIe 6.0/CXL3.0.

Synopsys: Harnessing AI and Photonic Integration

Accelerating Next-Level Innovation for TSMC Advanced-Node Designs

Synopsys collaborates with TSMC to improve chip design efficiency. They utilize artificial intelligence and photonic integrated circuit (PIC) technologies for this purpose.

TSMC is set to integrate Synopsys.ai suite to enable streamlined analog and digital design processes across its N3, N3P, and N2 process technologies. The integration includes using the DSO.ai platform, which automates chip design. It optimizes the balance between power, performance, and area in advanced chip designs.

One of the key objectives of this collaboration is the development of integrated radio frequency (RF) and photonic design flows. In modern processing, there’s a growing need for faster inter-chip communication. Photonic design offers a promising solution for higher data transmission rates and lower latency. Synopsys aims to use TSMC’s COUPE technology in its Photonic IC design and 3DIC Compiler toolsets to streamline the design and manufacturing of these components.

Furthermore, Synopsys has unveiled enhancements to its IP offerings tailored for TSMC’s advanced nodes. This encompasses a wide range of Foundation and Interface IPs, including UCIe, HBM4/3e, and PCIe 7.x/6.x.

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Siemens: Driving IC Verification for TSMC’s Latest Nodes

Image Credits: Siemens

Siemens EDA has achieved certification for several of its tools with TSMC’s latest semiconductor processes, including the advanced N2 process.

Among the key Siemens tools that have received certification is the Calibre nmPlatform tool suite.

The suite includes essential tools like Calibre nmDRC, Calibre nmLVS, Calibre Pattern Matching, and Calibre PERC. These tools are certified for TSMC N2, supporting the design of smaller, more efficient semiconductors.

Siemens Analog FastSPICE platform, known for its precision, is certified for TSMC’s N3P, N2, and N2P processes, verifying various circuits with accuracy.

In the realm of 3D integration, Siemens’ Calibre 3DSTACK solution has received approval to support TSMC’s 3Dblox standard. This standard acts as a guide for 3D IC designs and includes advanced thermal analysis for TSMC’s 3DFabric packaging. It helps designers predict and tackle overheating problems in densely packed ICs, ensuring performance and reliability in advanced nodes.

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Conclusion: Empowering Semiconductor Innovation

In the rapidly evolving semiconductor industry, TSMC’s advanced nodes are pushing boundaries. Collaboration with leading EDA companies like Cadence, Synopsys, and Siemens is crucial. They optimize EDA tools for TSMC’s latest process technologies. This empowers chip designers to unleash semiconductor innovation’s full potential. These partnerships enable advancements like 3D ICs and photonic integration. They pave the way for smaller, more powerful, efficient, and versatile semiconductor chips in the future.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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