Why does Intel want to Change Size of Photomasks?

Intel is pushing for a change in the size of photomasks, primarily motivated by the need to adapt to high-NA EUV lithography systems, especially in the post-2nm era.

Introduction:

The semiconductor industry is on the cusp of a transformative shift as Intel want to Change Size of Photomasks. This proposed change aims to introduce a 6- x 12-inch mask format, designed to facilitate the adoption of high-numerical aperture (high-NA) extreme ultraviolet (EUV) lithography. While the current 6- x 6-inch mask size will persist, the industry anticipates a gradual transition to the larger format to meet the demands of chip manufacturing in the post-2nm era, expected to commence around 2028.

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The Importance of Photomasks:

Photomasks, or masks, serve as master templates for unique chip designs and play a crucial role in semiconductor production. In lithography, a scanner places a mask where light passes through, creating patterns on a wafer. The manufacturing process transforms the wafer into chips. The size and quality of the mask are fundamental factors influencing the capabilities and efficiency of the lithography process.

Need for a New Mask Size:

The necessity to accommodate high-NA EUV lithography systems, particularly in the post-2nm era, drives the shift to a 6- x 12-inch mask size. Current EUV systems use a 0.33 numerical aperture (NA) lens with 13nm resolutions, while high-NA EUV scanners, still in research and development, feature a 0.55 NA lens with 8nm resolutions. To produce larger chips using high-NA EUV, the industry faces challenges such as the complex process of stitching together patterns printed on two masks.

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Benefits of 6- x 12-Inch Masks:

The proposed 6- x 12-inch mask size offers advantages in avoiding the stitching process when producing larger chips. Additionally, this simplification in the lithography process enhances efficiency and reduces the complexities associated with high-NA EUV lithography.

Challenges in Adoption:

While the benefits are evident, the transition to a new mask size poses significant challenges. The production of larger masks involves depositing alternating thin layers of silicon and molybdenum materials on a substrate, a process that becomes more intricate with the 6- x 12-inch format. Issues such as defects in the masks escalate the difficulties in manufacturing.

Read More: 3 Reasons Why TSMC Won’t Adopt High-NA EUV Lithography Until 2032

Industry Collaboration:

Intel’s push for the new mask size has garnered support from key players in the industry. IMS, a company that sells mask writers for 6- x 6-inch masks, will extend its support to the 6- x 12-inch format. Intel and TSMC, both shareholders in IMS, are among the proponents of the larger mask size. Lasertec, funded in part by Intel, is expected to provide support for the inspection of 6- x 12-inch masks.

Pellicles: A Crucial Component:

In the mask-making process, pellicles play a vital role in protecting the mask during various stages. The development of 6- x 6-inch pellicles posed challenges, and similar challenges are anticipated in creating pellicles for the future 6- x 12-inch format.

Conclusion:

Intel’s initiative to standardize a 6- x 12-inch mask size reflects the semiconductor industry’s commitment to advancing technology and addressing the challenges associated with high-NA EUV lithography. While the transition poses complexities, collaboration among industry players and advancements in technology promise a future where larger chips can be produced more efficiently, paving the way for innovations in semiconductor manufacturing.

Kumar Priyadarshi
Kumar Priyadarshi

Kumar Joined IISER Pune after qualifying IIT-JEE in 2012. In his 5th year, he travelled to Singapore for his master’s thesis which yielded a Research Paper in ACS Nano. Kumar Joined Global Foundries as a process Engineer in Singapore working at 40 nm Process node. Working as a scientist at IIT Bombay as Senior Scientist, Kumar Led the team which built India’s 1st Memory Chip with Semiconductor Lab (SCL).

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