TSMC to Build 1nm Transistors by 2030

Embark on a technological journey as TSMC unveils its roadmap set to revolutionize the semiconductor landscape. Delve into the details of their audacious plan to achieve 1nm transistors by 2030


The semiconductor industry is on the brink of a revolution, and Taiwan Semiconductor Manufacturing Company (TSMC) is leading the charge. Additionally,the global chip giant has recently shared its roadmap, outlining its ambitious goal of achieving 1nm transistors by 2030, enabling groundbreaking advancements in chip density and performance.

“TSMC has created a corporate vision board that showcases its plans for ambitious designs, enabling the utilization of up to a trillion transistors in a single package.”

In this article, we will delve into TSMC’s roadmap and explore the significance of these advancements, shedding light on the technical terms involved along the way.

At the recent IEDM conference, TSMC unveiled this audacious plan, showcasing its roadmap for the future.

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Monolithic Dies and Chiplets

TSMC’s roadmap envisions a future where monolithic dies could reach a staggering 200 billion transistors by 2030, a significant jump from the current industry standards.

To provide context, Nvidia’s largest monolithic TSMC die, the H100, currently boasts 80 billion transistors. A monolithic die refers to a single semiconductor substrate that houses all the necessary components of a microchip.

Additionally, TSMC’s roadmap showcases the growing prominence of chiplets, which are discrete semiconductor components that can be combined to form a larger chip.

Intel’s Ponte Vecchio chiplet, for instance, features a colossal 100 billion transistors, while AMD’s MI300 offers an impressive 146 billion transistors. Chiplets allow for greater flexibility in chip design and increased scalability, enabling the integration of more transistors and improved performance.

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Process Nodes: Advancing towards 1nm

To achieve these ambitious transistor counts, TSMC plans to progress through various process nodes, each representing a specific level of miniaturization and technological advancement.

Currently, TSMC is focusing on the 3nm process node, with production expected to continue until 2025. Following this, TSMC aims to transition to the 2nm process node, further reducing transistor dimensions and enhancing chip performance.

By 2028, TSMC anticipates reaching the 1.4nm (A14) process node. Finally, TSMC aims to pioneer the production of 1nm transistors by 2030, opening up possibilities for unprecedented levels of integration and chip performance.

The company will achieve this by leveraging an array of IC packaging technologies The industry is moving toward chiplet arrangements because they provide adaptability and cost savings.

TSMC is one step ahead, with plans to offer over 1 trillion transistors in 3D-packaged circuits and 200 billion in monolithic devices by 20303.

Additionally, Monolithic designs will eventually be limited to 200 billion transistors, which, while a large number, falls short of what chiplets offer. This is why TSMC is focusing on 3D Hetero Integration, which would have “one trillion transistors” by 2030.

Understanding Nanometer Terminology

To comprehend the significance of TSMC’s roadmap, it is crucial to understand the terminology related to nanometer measurements.

The nanometer (nm) is a unit of length used to quantify the size of transistors and other microscopic components on a chip.

The smaller the nanometer measurement, the more densely packed the transistors can be, leading to more powerful and energy-efficient chips.

Transitioning from larger process nodes to smaller ones, such as from 3nm to 2nm and eventually to 1nm, allows for a higher transistor count within a given area, providing tangible performance improvements and lower power consumption.

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TSMC vs. Intel: The Race for Technological Supremacy

Intel, a key player in the semiconductor industry, is also targeting the production of 1nm transistors by 2030. Encouragingly, TSMC’s roadmap aligns with Intel’s ambitions to leverage advanced packaging technologies and chiplets to enable the use of a trillion transistors on a single package.

Additionally, Intel plans to introduce its own 2nm process, called Intel 20A, in 2024, potentially leapfrogging TSMC in terms of technological advancements. This development signifies a significant milestone for Intel, as it seeks to regain its competitiveness in the semiconductor market.


As TSMC progresses through its roadmap, the industry as a whole stand to benefit from increased innovation, higher performance, and energy-efficient chips.

The race for technological supremacy with Intel adds an exciting dimension to the semiconductor landscape, with both companies driving towards the common goal of a trillion transistors on a single package.

As the industry inches closer to the era of 1nm transistors, the possibilities unprecedented levels of integration and chip performance will soon be a reality.

Editorial Team
Editorial Team
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