Introduction:
The semiconductor industry is witnessing a paradigm shift with the recent advancements in transistor technology. In a groundbreaking showcase at the IEEE International Electron Devices Meeting, three semiconductor giants – Intel, Samsung, and TSMC – presented their progress in developing complementary field-effect transistors (CFETs).
This blog post aims to provide an in-depth comparison of the CFET developments from these three industry leaders, exploring the unique features, innovations, and potential implications for the future of semiconductor technology.
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Complementary Field-Effect Transistors (CFETs) Overview:
CFETs represent a significant departure from the traditional FinFET structures, aiming to stack both n-type (nFETs) and p-type (pFETs) transistors on top of each other in a single, integrated process.
This design promises nearly double the transistor density, pushing the boundaries of CMOS logic and paving the way for the next phase in Moore’s Law.
FinFETs Vs CFETs
FinFET (Fin Field-Effect Transistor) and CFET (Complementary Field-Effect Transistor) are both transistor technologies, but they differ in their architectural design and the way they integrate n-type (nFET) and p-type (pFET) transistors.
Let’s explore the key differences between FinFET and CFET:
Design Structure:
- FinFET: FinFETs are named after their fin-like structure. In FinFET design, the gate wraps around a vertical fin of silicon, controlling the flow of current between the source and drain regions. The fin provides better control over the channel, reducing leakage current and improving overall performance.
- CFET: CFETs, on the other hand, adopt a 3D-stacked structure. They stack both n-type and p-type transistors on top of each other in a single, integrated process. CFETs aim to achieve nearly double the transistor density compared to FinFETs by combining both types of transistors in a more compact design.
Transistor Stacking:
- FinFET: FinFETs do not stack nFETs and pFETs directly on top of each other. Instead, they are side-by-side on the same silicon wafer, allowing for better control over electrical characteristics.
- CFET: CFETs stack nFETs and pFETs in a 3D configuration, utilizing both the upper and lower regions of the stack for different transistor types. This stacking enables a more efficient use of space and contributes to the potential for higher transistor density.
Advantages of CFET over FinFET:
- Density: CFETs aim to achieve higher transistor density, which is crucial for advancing semiconductor technology in line with Moore’s Law.
- Integration: The integration of nFETs and pFETs in a single stack simplifies the manufacturing process and may lead to more compact and power-efficient devices.
- Performance: The 3D-stacked design of CFETs has the potential to improve overall performance by reducing the distance between transistors and optimizing electrical characteristics.
Commercial Deployment:
- FinFET: FinFET technology has been in commercial use since around 2011 and is prevalent in modern semiconductor manufacturing processes.
- CFET: CFETs are still in the research and development phase, with experts estimating commercial deployment seven to ten years from now. There is ongoing work to address challenges before widespread adoption.
In summary, while FinFETs have been the dominant transistor technology for the past decade, CFETs represent the next evolution in transistor design. CFETs aim to overcome the limitations of traditional FinFETs by adopting a 3D-stacked structure, potentially leading to higher transistor density and improved overall performance in future semiconductor devices.
Intel’s CFET Advancements:
Intel, an early adopter of CFET technology, showcased several notable advancements in its CFET design. The company’s inverter circuits demonstrated a substantial reduction in size, with an innovative backside power delivery technology enabling interconnects both above and below the silicon surface.
Intel’s improvements included an increase in the number of nanosheets per device, a reduction in the separation between devices, and an optimized geometry for enhanced electrical characteristics.
Read more: Intel Breakthrough Industry First 3D Stack CMOS takes Moore’s law to New Heights
Samsung’s Innovative Approach:
Samsung, taking a unique approach, presented CFET prototypes with smaller contacted poly pitch (CPP) values of 48-nm and 45-nm. The company emphasized the critical aspect of electrical isolation between the stacked pFET and nFET devices, addressing potential issues related to current leakage.
Samsung’s decision to use a single nanosheet in each paired device, as opposed to Intel’s three, showcased a different strategy aimed at achieving enhanced CFET performance.
Read more: Samsung’s 3 nm Secret: GAA Transistors
TSMC’s Technological Breakthroughs:
TSMC demonstrated its CFET device with an industrially-relevant pitch of 48 nm, introducing a novel method for forming a dielectric layer between the top and bottom devices.
The company’s use of silicon germanium with a high fraction of germanium for the isolation layer showcased TSMC’s commitment to pushing the boundaries of semiconductor technology.
TSMC’s approach to isolating the two devices from each other highlighted their emphasis on technological precision.
Conclusion:
The comparison reveals that while Intel, Samsung, and TSMC share the common goal of advancing CFET technology, each company has adopted distinct strategies and innovations. Intel focuses on overall size reduction and backside power delivery, Samsung prioritizes electrical isolation, and TSMC emphasizes precision in dielectric layer formation. As the semiconductor industry collectively overcomes challenges, the collaboration and competition between these giants promise to shape the future of electronic devices and computing systems.
