CoWoS: TSMC's New Secret Weapon for Advanced Packaging

Introduction to CoWoS:

Taiwan Semiconductor Manufacturing Company (TSMC), renowned for producing the world’s most advanced microchips, is propelling the semiconductor industry forward through its ambitious expansion of Chip-on-Wafer-on-Substrate (CoWoS) manufacturing capacity.

Advanced packaging is gaining traction and can revolutionize microchip architecture. It involves linking, encasing, and safeguarding tiny silicon chips. This forms the foundation for stable operating systems needed in smarter AI devices and high-end applications.

This blog post explores how TSMC’s strides in CoWoS technology are set to redefine the industry’s strategic landscape and address the challenges posed by the evolving landscape of microchip miniaturization.

1. Why do we need Advanced Packaging Technology:

“Packaging” in computer chips involves assembling and connecting electronic components to create functional units such as processors or memory.

Moore’s Law initially predicted a transistor doubling on a microchip every two years. However, shrinking microchips has become increasingly difficult, challenging this principle.

To address this challenge, advanced packaging has emerged as a solution. The protective encasing around microchips plays a vital role in achieving high performance.

Given the minuscule dimensions of semiconductor features, chip designers now utilize advanced packaging techniques to boost processor performance without requiring further transistor shrinkage.

Advanced packaging technology is needed to meet the increasing demands of modern electronics. As chips become more powerful and complex, they require more interconnects and more power delivery. Advanced packaging technology can provide these capabilities in a smaller and more efficient form factor.

2. Chip-on-Wafer-on-Substrate (CoWoS):

CoWoS is an innovative packaging method that entails stacking multiple chips on top of each other on a wafer.

Wafer: A wafer is a thin slice of semiconductor material (typically silicon) on which electronic components are fabricated.

Chip-on-Wafer: This involves placing one chip on top of a wafer that contains other chips, allowing for efficient space utilization and enhanced performance.

Substrate: The substrate serves as a base or platform that supports and connects the stacked chips, providing a foundation for their integration and collaborative functionality.

Image Credit: AnandTech

3. Importance of CoWoS:

Now, let’s explore why CoWoS is a game-changer in the world of electronic packaging.

Space and Efficiency: CoWoS optimizes space utilization on a single wafer by stacking multiple chips. This is vital for achieving higher computing power within a smaller physical footprint, especially crucial for compact devices like smartphones and tablets.

Improved Performance: Stacking chips closely and minimizing inter-chip distances enhances communication and data transfer speed, ultimately boosting the overall performance of the integrated system.

Reduced Power Consumption: Physical proximity of chips in CoWoS reduces the power needed for communication between them, leading to more energy-efficient devices.

Cost-Effectiveness: Despite its complexity, CoWoS contributes to cost-effectiveness by optimizing resource use and improving the yield of usable chips.

4. 3D Packaging Vs CoWoS

CoWoS (Chip-on-Wafer-on-Substrate) and 3D IC (Integrated Circuit) packaging are advanced packaging technologies. They aim to achieve three-dimensional integration of chips, but they take different approaches.

CoWoS involves stacking chips on a wafer and integrating them onto a substrate for efficiency and improved performance.

3D IC packaging directly stacks and bonds chips on top of each other for more versatility in integration and enhanced performance.

Let’s explain the differences in simpler terms:

CoWoS (Chip-on-Wafer-on-Substrate):

In CoWoS, chips are first fabricated separately on individual wafers. Then, these chips are stacked or layered on top of each other, with one chip on the top connected to the underlying wafer containing other chips. Finally, they are integrated onto a larger support structure or substrate.
The focus in CoWoS is on stacking chips on a single wafer and integrating them with a substrate, optimizing the use of space and improving performance.

3D IC (Integrated Circuit) Packaging:

In 3D IC packaging, multiple layers of chips are directly stacked or bonded on top of each other. These chips can be different or identical in terms of functionality.
The integration in 3D IC packaging is typically achieved by using specialized techniques to connect and communicate between the stacked layers of chips, forming a cohesive 3D structure.
The primary goal in 3D IC packaging is to enhance performance, reduce power consumption, and improve overall system efficiency by leveraging the vertical dimension.

What are the Key Differences between CoWoS and 3D IC packaging:

Integration Approach: CoWoS involves stacking chips on a single wafer and then integrating them onto a substrate. In contrast, 3D IC packaging directly stacks and bonds chips on top of each other.

Wafer Usage: CoWoS primarily uses a single wafer for stacking chips, whereas 3D IC packaging involves stacking chips from different wafers.

Complexity and Flexibility: 3D IC packaging can be more complex in terms of interconnections between layers, but it offers greater flexibility in mixing and matching different chips with varying functionalities. CoWoS, on the other hand, focuses on stacking chips manufactured on a single wafer, making it more straightforward.

Use Cases: CoWoS is often used for integrating chips that are related or complement each other’s functionality (e.g., processor and memory). 3D IC packaging is more versatile and can be used for various applications, including integrating heterogeneous chips for specialized functions.

In summary, CoWoS stacks chips on a wafer and integrates them onto a substrate for space and performance benefits.

On the other hand, 3D IC packaging directly stacks and bonds chips, offering flexibility and efficiency for enhanced performance.

Which companies are working in this area:

As of my last knowledge update in September 2021, various companies are actively working on advanced packaging technologies like CoWoS (Chip-on-Wafer-on-Substrate) and 3D IC (Integrated Circuit) packaging to enhance performance, reduce power consumption, optimize space utilization, and enable new functionalities. Here’s an overview of some companies and the technologies they are involved in:

TSMC (Taiwan Semiconductor Manufacturing Company):

TSMC is a leading semiconductor manufacturing company actively working on CoWoS and other advanced packaging technologies. CoWoS is a critical offering from TSMC, enabling efficient stacking of chips on a wafer and integration onto a substrate. TSMC is focused on this technology to optimize chip integration, improve performance, and reduce power consumption in various electronic devices.

Intel:

Intel is investing heavily in 3D IC packaging technologies, such as Foveros and Omni-Directional Interconnect (ODI). Foveros allows for stacking different chiplets (functional components of a chip) vertically to create 3D integrated devices, enhancing performance and power efficiency. Intel aims to use these technologies to address the growing demand for more powerful and energy-efficient computing solutions.

Samsung Electronics:

Samsung is actively working on both CoWoS and 3D IC packaging technologies. Samsung’s offerings include “X-Cube” and “I-Cube” for 3D IC integration. These technologies are designed to enable stacked memory solutions, heterogeneous integration, and multi-chip modules. Samsung focuses on these technologies to improve system performance, reduce power consumption, and optimize space in advanced electronic devices.

GlobalFoundries:

GlobalFoundries is also investing in advanced packaging technologies, including 3D IC integration. They are developing technologies like 3D FOWLP (Fan-Out Wafer Level Packaging) and 3D Chip Stacking to enable multi-die integration for enhanced performance, power efficiency, and miniaturization.

These companies are investing in advanced packaging technologies to address the challenges posed by the limitations of traditional 2D chip integration. Advanced packaging technologies like CoWoS and 3D IC packaging offer solutions to achieve better performance, power efficiency, and miniaturization, meeting the demands of modern electronic devices such as smartphones, laptops, data centers, and IoT (Internet of Things) devices. Each company’s approach aligns with its strategy to provide cutting-edge semiconductor solutions for a wide range of applications.

Conclusion:

In the rapidly evolving semiconductor industry, TSMC stands out with its proactive and forward-looking strategies. Anticipating potential technological barriers that could impede the growth of AI applications, the company took the initiative to launch advanced packaging programs like CoWoS as early as 2009 under the guidance of Shang-Yi Chiang. This foresight was well ahead of the realization that packaging would become a pivotal element in the future of semiconductors.

As a result, TSMC’s CoWoS technology has become a pivotal player in the production of AMD’s Instinct MI300 advanced chiplets. Moreover, Nvidia’s choice to manufacture its H100 with TSMC solidifies their strong reliance on the company, given TSMC’s exclusive capability for high-volume manufacturing of such designs at a reasonable cost. Consequently, Nvidia and AMD collectively represent a substantial share of TSMC’s CoWoS production capacity.

Reference: Advanced Packaging’s Next Wave by Semi Engineering