Introduction
The semiconductor industry has long been driven by the relentless pursuit of smaller, more powerful computer chips. However, the limitations of traditional silicon-based chips have prompted researchers to explore alternative materials and innovative fabrication techniques.
In a groundbreaking study published in the journal Nature, Jayachandran presented a significant advancement in semiconductor technology by demonstrating the fabrication of 3D computer chips using ultrathin 2D materials, specifically molybdenum disulfide (MoS2) and tungsten diselenide (WSe2).
Follow us on Linkedin for everything around Semiconductors & AI
The 2D Materials Revolution
Silicon, the stalwart of semiconductor technology, is reaching its limits in accommodating the increasing demand for smaller and more powerful chips. The concept of 2D materials, first introduced with graphene, gained attention but faced limitations in practical semiconductor applications due to challenges in inducing semiconducting properties.
However, researchers are now turning to alternatives like molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), which offer promising semiconductor properties without the same difficulties encountered with graphene.
Read More –World’s First Functional Semiconductor Using Graphene is Here! – techovedas
What’s special about these materials?
Molybdenum disulfide (MoS2) and Di selenide (WSe2) are semiconducting Transition Metal DiChalcogenides (TMDC).
Advantages of TMDCs: –
TMDCs are known for their semiconducting properties, high surface-to-volume ratio, and strong light-matter interaction.
Charge carrier mobility: TMDCs have good charge carrier mobility and low-temperature integration.
Mechanical flexibility: They are mechanically flexible and have an ultra-thin, flat, almost defect-free surface.
TMDCs are chemically stable.
MoS2 is known for its high thermal stability and excellent electrical conductivity, making it a promising material for high-temperature devices. Similarly, and tungsten Di selenide (WSe2) is known for its high electron mobility and high carrier density, making it a promising material for use in optoelectronic devices.
The Challenge of Moore’s Law
The era of ‘More than Moore’ represents a shift in the semiconductor industry. For decades, advancements were driven by Moore’s Law, which predicted that the number of transistors on a chip would double approximately every 18 months.
This led to faster processors and increased data storage. However, as the physical dimensions continue to shrink, the costs for system-on-chip development in advanced CMOS technology are skyrocketing, and Moore’s Law will eventually reach its limit.
In response to these challenges, the industry is moving towards integrating non-digital components into standard computer chips. This includes technologies such as analog/mixed-signal, high-voltage, and ultra-low-power.
The shift towards these multi-technology devices is driven by consumer demand for new smart products, environmental awareness for green solutions, and the need for innovation in areas like medical devices.
Read more –What is Moore’s Law, More than Moore, and Beyond Moore? – techovedas
Building Tiered 3D Chips: Challenges
One proposed solution to the ‘more than Moore’ challenge is the development of tiered 3D chips. However, creating these structures presents difficulties as processing conditions vary between layers.
For instance, the top layers must not exceed temperatures of around 450 °C, posing a challenge for traditional semiconductor processing. Additionally, the underlying layers can introduce rough surfaces that compromise the quality of subsequent layers.
Figure: Fabrication process of a 3D chip from 2D materials
The 3D Breakthrough with 2D Materials
Fig: Fabrication Steps
In a groundbreaking study, Jayachandran and colleagues present a novel approach to building 3D computer chips using ultrathin 2D materials. They successfully fabricated a wafer with two integrated tiers of nanoscale transistors, each layer containing over 10,000 transistors made from single-atom-thick sheets of MoS2.
Crucially, the researchers overcame the processing challenges by growing the MoS2 films separately and then transferring them to the wafer, a process that avoids high temperatures.
a. Schematic of the potential for 3D integration of 2D FETs in ‘More Moore’ and ‘More than Moore’ technologies.
b. electron microscopy image showing the cross-section of a three-tier 3D integrated circuit based on 2D transition-metal dichalcogenide.
c. scanning electron micrograph of a 2D FET with channel length, LCH = 45 nm, and contact length, LC = 90 nm, from a two-tier 3D integrated circuit with more than 200 aggressively scaled devices.
d. Optical image showing wafer-scale monolithic two-tier 3D integration of 2D FETs with more than 10,000 devices in each tier
Read More: What is 2D, 2.5D & 3D Packaging of Integrated Chips? – techovedas
Versatility and Scalability
The researchers went a step further, demonstrating the versatility of their process by constructing a three-tier structure combining MoS2 transistors with those made from WSe2. Remarkably, all transistors maintained high performance across each level.
Moreover, the team scaled down the transistors in a two-tier configuration, achieving channels as small as 45 nanometers – a significant advancement in miniaturization.
Figure – A 3D circuit made from 2D materials.
The Integration Challenge
The process of building an integrated computer circuit involves two main phases: the ‘front end of the line’ (FEOL), where components like transistors are patterned into the semiconductor chip, and the ‘back end of the line’ (BEOL), traditionally associated with wiring components together.
With the emergence of ‘more than Moore,’ BEOL takes on a new role, incorporating functionalities like sensing capabilities. This requires the use of semiconducting materials compatible with BEOL processes, making 2D materials highly relevant.
In particular, the study by Jayachandran has made significant strides in establishing the relevance of 2D materials in the BEOL process.
The authors produced and characterized around 20,000 functional devices, providing compelling evidence that 2D materials are an excellent candidate for next-generation transistor channels.
Additionally, the study demonstrated that memory devices and photodetectors can be realized on a large scale with 2D materials, indicating their potential to deliver ‘more than Moore.’
Challenges and Future Directions
Despite the remarkable progress, challenges remain. The researchers’ transistors are ‘back-gated,’ where the entire channel is controlled by a gate beneath it. Incorporating a gate dielectric on top of the channel to enhance transistor performance is a next-step requirement, but available technology is not yet suitable for the 3D design. 
The roadmap envisions developing devices entirely enveloped by a gate for strong electrostatic control, demanding improvements in gate technology for 2D channels.
Unanswered Questions
While the study reports tens of thousands of functional transistors, certain questions linger. The potential impact of factors like drain-induced barrier lowering on device performance remains unclear.
This phenomenon involves the drain competing with the gate for control of the channel. Clarifying these issues is crucial for determining whether these devices are ready to realize the roadmap beyond silicon.
Read more – Explained: What the hell is 3D IC packaging?
Conclusion
In conclusion, the research by Jayachandran and colleagues represents a pivotal moment in the journey towards 3D computer chips using 2D materials. Their innovative approach, overcoming traditional processing challenges, demonstrates the versatility and scalability of 2D materials. While some challenges persist, the extensive evidence presented in the study positions 2D materials as more than an academic curiosity. The semiconductor industry now has tangible proof that 2D materials could usher in the next era of transistor channels, paving the way for fully functional 3D computer chips.
