Sub-5nm Chips: Huawei Tests Brute Force Method to Circumvent US Restrictions

7nm lithography+ SAQP may exhibit performance characteristics similar to or better than those manufactured with conventional 5nm lithography.
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In the ever-evolving landscape of technology, the race for advanced computer chips has been a pivotal battleground. At the forefront of this race is Huawei, the Chinese tech giant, which is pioneering a novel approach to chip manufacturing known as Self-Aligned Quadruple Patterning (SAQP). This method, though considered “brute-force” due to its lesser precision compared to existing techniques, holds the potential to revolutionize chip production and potentially circumvent restrictions imposed by the United States on China’s access to Huawei Sub-5nm Chips.

Despite utilizing 7nm lithography equipment, the chips produced with SAQP may exhibit performance characteristics similar to or better than those manufactured with conventional 5nm lithography.

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Understanding SAQP: Huawei Sub-5nm Chips

SAQP, or Self-Aligned Quadruple Patterning, represents a departure from conventional chip fabrication methods primarily in its approach to patterning. Traditional lithography techniques rely on precise and intricate patterning processes to define features on semiconductor chips. These processes involve complex steps to accurately transfer patterns onto the silicon substrate, often requiring meticulous control over parameters such as exposure dose and focus.


In contrast, SAQP adopts a more robust approach by utilizing quadruple patterning. This means that instead of relying on a single set of patterns to define features, SAQP employs a series of overlapping patterns. By strategically aligning and overlapping these patterns, SAQP achieves the desired feature definition on the chip.

How SAQP Works?

In semiconductor manufacturing, engineers use the technique of Self-Aligned Quadruple Patterning (SAQP) to define very small features on silicon wafers. It’s particularly useful in advanced nodes where traditional lithography techniques face challenges due to the limitations of optical resolution.

Here’s a simplified explanation of how SAQP works:

  1. Initial Patterning: The process begins with an initial lithographic step where a sacrificial pattern is created on the wafer. This pattern is typically larger than the final desired feature size.
  2. Spacer Deposition: Next, a spacer material is deposited uniformly across the wafer surface. This spacer material adheres to the sidewalls of the sacrificial pattern but does not cover the spaces between the patterns.
  3. Etching: The wafer undergoes an etching step, where material is selectively removed. This process removes the sacrificial pattern, leaving behind only the spacer material on the sidewalls.
  4. Second Spacer Deposition and Etching: Another round of spacer deposition and etching is performed. This further reduces the width of the spacer material on the sidewalls.
  5. Final Patterning: The final step involves removing the spacer material, leaving behind a smaller pattern defined by the spacer dimensions. This pattern corresponds to the desired feature size.

The key principle behind SAQP is the self-alignment of the spacer material, which determines the final feature size.

Image Credits: SemiWiki

Here’s why SAQP is effective:

Resolution Enhancement: SAQP allows for the creation of features that are smaller than what traditional lithography techniques can achieve. By leveraging the self-alignment of spacer materials, SAQP improves the resolution of the patterning process.

Control Over Feature Size: The thickness of the spacer material and the number of spacer deposition and etching cycles determine the dimensions of the final features. This provides a high level of control over feature size, critical for advanced semiconductor nodes.

Parallel Processing: SAQP enables high-throughput manufacturing by concurrently performing on multiple regions of the wafer.

While SAQP offers advantages in terms of resolution and control over feature size, it also introduces complexity to the manufacturing process and requires careful optimization of parameters to ensure uniformity and reliability across the wafer.

The Promise of SAQP for Huawei Sub-5nm Chips

Suppose a semiconductor manufacturer in China(SMIC) has access to lithography equipment capable of producing features down to 7nm, but they face challenges in competing with manufacturers using more advanced lithography technologies, such as 5nm or below, due to limitations in their equipment.

With SAQP, this Chinese manufacturer can leverage their existing 7nm lithography capability to achieve feature sizes comparable to those produced using more advanced lithography technologies. Here’s how:

Utilizing SAQP: Instead of relying solely on the 7nm lithography capability, the manufacturer can implement SAQP techniques. By applying multiple rounds of spacer deposition and etching, they can effectively reduce the feature sizes beyond what is achievable with their lithography equipment alone.

Feature Size Reduction: Through SAQP, the manufacturer can shrink the feature sizes produced by their 7nm lithography equipment to levels approaching 5nm or even smaller. This allows them to compete with manufacturers using more advanced lithography technologies in terms of feature size, critical for performance and efficiency in semiconductor chips.

Cost-Effective Approach: SAQP enables the manufacturer to achieve advanced feature sizes without the need to invest in costly next-generation lithography equipment, such as extreme ultraviolet (EUV) lithography. This can significantly reduce capital expenditure and operational costs, making chip production more economically viable.

It’s likely that semiconductor manufacturers have utilized SAQP in the fabrication process to create the fins in 7nm technology chips. This adoption isn’t entirely surprising, as SAQP has been increasingly favored for crafting intricate features in advanced semiconductor nodes.

What’s noteworthy here is the application of SAQP to the metal layers of the chip. Metal layers are used for interconnections and wiring between different components of the semiconductor device.

Applying SAQP to these metal layers indicates a significant advancement because it allows for the creation of even smaller and more precise features in the wiring, enabling higher performance and efficiency in the semiconductor device.

Huawei Sub-5nm Chips & Collaborations

Leading the charge in SAQP research and development is Huawei, backed by its considerable resources and expertise in the field of technology. However, Huawei is not alone in this endeavor.

Collaborating with a Chinese state-backed company, SiCarrier, and an enigmatic partner named Naura, Huawei is pooling its resources to advance SAQP technology.

This collaborative effort underscores the strategic importance of SAQP in China’s quest for technological autonomy.

Challenges and Considerations

While SAQP holds immense promise, it is essential to temper expectations with a dose of realism. As of now, SAQP is still in the developmental stages, with its effectiveness for mass production yet to be conclusively demonstrated.

Moreover, SAQP chips may not match the efficiency or performance of those produced using more advanced techniques. As such, while SAQP represents a significant step forward for China’s chip industry, it is not without its limitations and challenges.


Huawei’s pursuit of the SAQP method signifies a bold and innovative approach to chip manufacturing. By embracing a “brute-force” methodology, Huawei aims to reshape the semiconductor landscape and potentially alleviate some of the technological constraints imposed by external forces. As the journey towards SAQP continues, the global semiconductor industry watches with anticipation, recognizing the potential for a seismic shift in chip manufacturing paradigms.

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