Top EDA Tools in Each Step of ASIC Design Flow

Although, for seamless operation, it is advisable to be loyal to one EDA suite for a project but industry level designs demand the least time to market and precision. Hence, we use different EDA tools for different steps in the ASIC design flow.

What is EDA?

Electronic Design Automation (EDA) is a category of software tools that are used for designing ASIC . These systems can range from integrated circuits to printed circuit boards.

The tools in EDA work together in a design flow that chip designers use to design and analyse entire semiconductor chips. Due to the complexity of physical designs, circuit behaviour, and logical designs, EDA tools are essential.

They help automate the design, verification, and testing processes. This automation helps reduce the time it takes for a product to reach the market and also improves the quality of the design.

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An analogy to understand EDA

Imagine you’re an architect tasked with designing a skyscraper. Instead of manually sketching every detail, you have access to sophisticated computer-aided design (CAD) software.

This software allows you to create, modify, and analyze the building’s blueprints in a much more efficient and error-free manner.

It helps you optimize the structure for strength, plan the layout for maximum efficiency, and simulate various conditions like wind and earthquakes to ensure the building’s stability.

In this analogy:

  1. Skyscraper Design = Electronic System Design (ICs, PCBs, etc.)
  2. Architect = Electronic Engineer or Designer
  3. CAD Software = Electronic Design Automation (EDA) Tools

Just as CAD software streamlines the architectural design process, EDA tools streamline the electronic design process by providing tools for schematic capture, simulation, layout, verification, and more. These tools significantly reduce the time and effort needed to design and test electronic systems, ensuring designers meet specifications and can reliably manufacture them.

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EDA tools for each step of ASIC design flow:

There is a plethora of EDA tools available in the market. Likes include Cadence suite, Synopsys, Mentor Graphics etc. Although, for seamless operation, it is advisable to be loyal to one EDA suite for a project but industry level designs demand the least time to market and precision. Hence, we use different EDA tools for different steps in the ASIC design flow.

In this article we shall explore the best EDA tools for every step of design flow.

RTL Design & Simulation:

RTL (Register Transfer Level) design engineer converts the specification into an RTL code using the HDL (Hardware Description Language) generally either in Verilog or VHDL. After writing the RTL code, the RTL designer simulates the code in an RTL Simulator to check the design’s functionality. They create various testbenches at this stage to verify the design’s functionality under different conditions.

VCS by Synopsys is often considered the best for this step due to its high performance, capacity, and low total time to results. It provides fast simulation for both single-core and multi-core configurations, making it ideal for complex designs.

Logic Synthesis:

In this step, the design team converts a high-level description of the design (RTL Code) into an optimized gate-level representation using a specific standard cell library and incorporating defined design constraints.The output of this step is a gate-level netlist of a particular standard cell library.

Fusion Compiler by Synopsys is often used because it provides superior quality of results and convergent design closure. It integrates RTL-to-GDSII tools into a unified flow, enabling faster convergence with better QoR (Quality of Results).

LEC (Logic Equivalence Check):

This is done to make sure that there are not logical changes occurred during the synthesis. It ensures that the synthesized design is logically equivalent to the RTL design.

Conformal by Cadence is preferred because it provides comprehensive and high-performance equivalence checking. It ensures that the RTL and gate-level netlists are functionally identical, reducing the risk of functional errors.

Static Timing Analysis:

STA is a method used in digital circuits to validate the timing performance of a design1. It checks all possible paths for timing violations by breaking down a design into timing paths, calculating the signal propagation delay along each path, and checking for violations of timing constraints.

PrimeTime by Synopsys is often used because it provides comprehensive analysis and signoff of timing, signal integrity, and power. It offers fast, accurate, and comprehensive timing and signal integrity (SI) analysis, enabling designers to achieve timing closure faster.

DFT (Design for Testability) Insertion:

This is done in this stage to verify the chip after fabrication is done. It involves adding additional circuitry i.e., scan cells to the design to make it easier to test and to increase the coverage of the testing process.

Synopsys’ DFT Compiler is a comprehensive solution for implementing various DFT methodologies such as SCAN chain insertion, test point insertion, compression insertion, boundary scan insertion, and core wrapping. It is useful for multi-level compressor-decompressor architecture implementation, which can be helpful in optimizing test data volume and test time.

One of the key reasons for its popularity is its ability to seamlessly integrate with other Synopsys tools, providing a complete flow from design to test. This allows for a smooth transition from design to test preparation, reducing the overall design cycle

Place and Route (PnR):

The goal of PnR stage is to place all the standard cells, Macros and I/O pads with minimal area, with minimal delay and Route them together in such a way that there is no DRC (Design Rule Check) error. The final output of this stage is the layout of design in the form of GDSII file.

Innovus by Cadence is often chosen because it provides a fast, power-efficient integrated physical design solution. It uses a massively parallel architecture to provide scalability and speed, enabling designers to handle large, complex designs.

RC Extraction:

After completing the Place and Route (PnR) step, the design extracts into an RC (resistance-capacitance) network. Post-layout simulation and analysis, including Static Timing Analysis (STA), then use this RC network to ensure the design meets its timing, power, and performance goals.

Quantus RC Extraction by Cadence is popular because it provides best-in-class accuracy and performance. It ensures accurate parasitic extraction, which is critical for achieving timing and signal integrity goals.

Physical Verification:

This is the final step before the design is sent for manufacturing. It involves checking the design for manufacturability, reliability, and electrical issues. It ensures that the design meets all the foundry-specific layout rules.

Physical verification involves three steps, namely:

  1. Design Rule Check (DRC): DRC determines if a chip layout satisfies a number of rules as defined by the semiconductor manufacturer
  2. Electrical Rule Check (ERC): ERC verifies the correctness of power and ground connections, and that signal transition times (slew), capacitive loads and fanouts are appropriately bounded

Ansys is an emerging provider of simulation software that engineers use to design and analyse complex systems.

Ansys supports ASIC design flow. Tools for power, signal, thermal integrity, ESD, and more.
Handles complex Multiphysics problems in ASICs. Variability in on-chip scenarios managed effectively.

3. Layout Versus Schematic (LVS):

LVS verifies the functionality of the design. The design derives a netlist from the layout and compares it with the original netlist from logic synthesis or circuit design. Siemens’ Calibre is often considered one of the best tools for overall Physical Verification. It excels in handling complex designs and large data volumes, making it suitable for advanced process nodes due to its high performance.

Another reason is its wide acceptance in the industry. Many foundries provide rule decks for Calibre, ensuring that the checks performed are accurate and up-to-date with the latest process requirements.

Tape-out:

In the final step of the design process, designers hand off the design data to the foundry for manufacturing. This step involves generating the final data files required by the foundry to manufacture the ASIC.

In the tape-out process, designers use Calibre to perform final checks on the design before sending it for manufacturing. Calibre checks for any violations of manufacturing process rules. If violations are found, designers must fix them before the design can be taped out. Calibre’s comprehensive checking capabilities make it an invaluable tool in this process.

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Conclusion

The ASIC design flow outlined predominantly relies on EDA (Electronic Design Automation) tools from industry leaders Synopsys and Cadence. Designers favor Synopsys tools like VCS, Fusion Compiler, and PrimeTime for RTL design, logic synthesis, and static timing analysis. Cadence’s Innovus and Quantus RC Extraction excel in place and route as well as post-layout extraction. Siemens’ Calibre enjoys widespread adoption in physical verification.

Editorial Team
Editorial Team
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