Introduction
Nanosheets & Nanowires transistors have garnered significant attention due to their potential to drive future low-power VLSI and address the challenges associated with scaling transistors to sub-5-nanometer logic devices. In this article, we will delve into the technical details of these emerging transistor technologies, exploring their potential impact on the semiconductor industry.
Introduction to Emerging Transistor Technologies
The semiconductor industry has witnessed a continuous quest for innovation, driven by the need for higher speed, energy efficiency, and integration density of integrated-circuit products. The downscaling of transistors while keeping power consumption low has become increasingly challenging, prompting the exploration of novel materials and device architectures. In this context, emerging Gate All Around transistor technologies such as nanowire and nanosheet transistors have emerged as promising candidates for sub-5-nanometer logic devices.
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Limitations of FinFET that let to development of GAA-FET
The limitations of FinFET technology that led to the development of gate-all-around (GAA) transistors include challenges related to the
3D structure-induced large parasitic capacitance
Mechanically unstable high-aspect-ratio fins
Difficulties in forming high-k metal gate (HKMG)
High-k metal gate (HKMG) technology improves transistors in integrated circuits by employing high-k dielectrics with higher permittivity and metal gate electrodes. This enhances performance and energy efficiency, especially in designs like FinFET.
Additionally, the small fin pitch makes it challenging to implement HKMG formation and raised crystal growth between source/drain known as epitaxy. Furthermore, the minimum fin width (thickness) is limited to about 4 nm, beyond which device performance undergoes rapid degradation.
These limitations indicate that FinFET technology might find it difficult to survive when the physical gate length becomes smaller than 10 nm. In response to these limitations and with the aim of enhancing device performance at smaller technology nodes, researchers have actively pursued the development of GAA transistors, including nanosheets and nanowires.
Figure – The advantages of Vertically Stacked Nanosheets with respect to FinFET in terms of effective device width (Weff)
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Fundamentals of Nanowire and Nanosheet Transistors
Gate All Around (GAA) transistors can be based on either nanowires or stacked nanosheets, aligned either parallel or perpendicular to the substrate. Since 2017, according to Huiming Bu, director of advanced logic and memory technology at IBM’s AI Hardware Centre, the industry consensus has gradually converged on horizontally stacked nanosheets as the best alternative for the 5nm generation. These devices start with alternating layers of silicon and SiGe, patterned into pillars.
What are Nanowire transistors?
In nanowire transistors, the channel through which current flows consists of one or more nanowires, typically made from materials like silicon, germanium, or gallium nitride. The small size of the nanowires allows for excellent control of the electric field within the transistor, which can lead to better performance and lower power consumption compared to traditional planar transistors. Various applications leverage their utility, incorporating nanosheets and nanowires in realms like sensors, quantum computing, and nanoscale electronics.
Nanowire transistors characterized by their gate-all-around structure, have shown superior electrostatics and increased current drive capability. The vertically stacked nanowire (VSNW) and laterally packed nanowire (LPNW) FETs have demonstrated enhanced performance, making them attractive options for next-generation transistor technologies.
In the case of VSNW FETs, imagine stacking Lego blocks on top of each other to create a vertical tower. This structure allows for the relaxation of the channel length scaling and reduces area and cost without a leakage penalty. On the other hand, comparing LPNW FETs to laying down a row of bricks side by side creates a horizontal structure.
Why to stack GAAs horizontally or vertically?
The need for vertically or horizontally stacking nanowires or nanosheets in field-effect transistors (FETs) arises from the desire to enhance the current drive capability and optimize the performance of the transistors. Such arrangement offers more surface area for current conduction. Researchers have developed Vertically Stacked Nanowire (VSNW) FETs and Laterally Packed Nanowire (LPNW) FETs, along with Vertically Stacked Nanosheet (VSNS) FETs and Laterally Packed Nanosheet (LPNS) FETs to address these needs.
The above figure shows the schematics of FinFET, Vertically Stacked & Laterally Packed NanoWire (notice blue cylinder like nanowires) and Vertically Stacked and Laterally Packed NanoSheets (notice stacked blue sheets).
What are Nanosheet transistors?
Nanosheet GAA transistors, or Gallium Arsenide Nanosheets (GANS), are a type of transistor that utilizes individual nanosheets of Gallium Arsenide (GaAs) to create high-performance, compact electronics. The material may differ from GaAs as per use case.
Additionally, Traditional transistors have used a planar design, where the gate material lies flat on the semiconductor surface. In contrast, nanosheet transistors employ a three-dimensional structure, using thin horizontal sheets (nanosheets) of semiconductor material stacked vertically. This design helps improve control over the flow of electrons as multiple nanosheets provide more surface area for current conduction, resulting in higher drive current and performance.
Advantages of nanosheets:
1-These devices also offer multiple threshold and isolation solutions inherited from FinFET technologies. The performance improvement is characterized by their ability to provide increased effective width (Weff) per active footprint, better electrostatics at aggressive gate lengths
2-The devices also demonstrate good electrostatics for nFET and pFET with ultra-thin 5nm silicon channels, as well as the ability to modulate threshold voltages and suppress sub-sheet leakage.
3-Additionally, the devices show improved performance through the use of wrap-around contact (WAC) for extrinsic resistance reduction. These features are characterized through various measurements and analyses, including Id/Vg characteristics, TEM micrographs, and electrical verification of threshold voltage modulation.
Challenges and Opportunities
Despite the promising potential of nanowire and nanosheet transistors, there are challenges that need to be addressed. Additionally, The integration of novel materials and device architectures requires careful consideration of parasitic resistances, capacitances, and reliability issues.
1.Manufacturing Complexity:
Nanosheet Assembly: The fabrication of nanosheet structures can be intricate, requiring precise control over the deposition and alignment of the nanosheets.
Uniformity: Achieving uniformity in the size, shape, and placement of nanowires or nanosheets across a large-scale manufacturing process can be challenging.
2.Material Properties:
Material Selection: At the nanoscale, the properties of materials can differ significantly from their bulk counterparts. For instance, quantum effects become more pronounced. Electronic, thermal, and mechanical properties may exhibit size-dependent behaviours.
Strain Effects: As devices scale down, strain effects become more significant, impacting the performance of semiconductor materials.
3.Process Integration:
Compatibility: Integrating GAA nanowires or nanosheets into existing semiconductor processes may require adjustments or entirely new manufacturing techniques.
Yield Issues: Achieving high yields in mass production can be challenging due to the increased complexity of the manufacturing process.
GAAFETs in News and future
The technology that follows GAAFET (Gate-All-Around Field-Effect Transistor) is the 3 nm process. This is the next die shrink after the 5 nm technology node.
South Korean chipmaker Samsung started shipping its 3 nm GAA process, named 3GAA, in mid-2022. Samsung’s 3 nm process is based on GAAFET technology, a type of multi-gate MOSFET technology. Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (Multi-Bridge Channel Field-Effect Transistor)
On the other hand, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node termed N3 is under way with good yields
Beyond-MOSFET future
The technology that is expected to succeed GAAFETs (Gate-All-Around Field-Effect Transistors) is RibbonFET. RibbonFET is Intel’s implementation of GAAFET and is expected to be introduced with the 20A process, likely to be productized by the end of 2024.
RibbonFETs are a type of GAAFET with a flexible width transistor and a number of layers helping drive transistor current1. They enable a single fin of variable length, allowing the current for each individual cell device to be optimized in power, performance, or area.
Conclusion
In conclusion, nanowire and nanosheet transistors represent a significant leap forward in transistor technology, offering the potential to drive future low-power VLSI and address the challenges associated with scaling transistors to sub-5-nanometer logic devices. As research and development in this field continue to progress, the industry is poised to witness the transformative impact of these emerging transistor technologies on the future of information technology.
