2X Bigger, 12X Hungrier for Power: TSMC to Build Massive Chips with SoW by 2027

TSMC to build massive chips twice the size of today's largest — chips will use thousands of watts of power.
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In a groundbreaking announcement that has sent shockwaves through the semiconductor industry, TSMC has unveiled plans to develop massive chips twice the size of today’s largest processors.

These colossal chips, measuring 12 HBM4E Stacks by 2027, mark a significant leap forward in computational capability and complexity.

With the potential to revolutionize industries ranging from artificial intelligence to high-performance computing, TSMC’s ambitious endeavor promises to redefine the boundaries of what is possible in the realm of semiconductor technology.

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The Evolution of CoWoS Technology for TSMC Chips:

At the heart of TSMC groundbreaking initiative lies its chip-on-wafer-on-substrate (CoWoS) packaging technology, which has undergone significant advancements in recent years.

Take, for example, the latest iteration of CoWoS, showcased at TSMC’s North American Technology Symposium. This technology enables the construction of silicon interposers that are over three times larger than a standard photomask.

With this capability, imagine a medical imaging system that integrates multiple chiplets, enabling faster and more accurate diagnosis of diseases such as cancer.

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The Road to Monstrous Packages for TSMC Chips:

The latest iteration of CoWoS technology now permits TSMC to fabricate silicon interposers approximately 3.3 times larger than a standard photomask, which measures 858mm2. Consequently, this advancement allows for the integration of logic, eight HBM3/HBM3E memory stacks, I/O components, and other chiplets within an area of up to 2831 mm2. The maximum substrate size for this technology is 80×80 mm. Both AMD’s Instinct MI300X and Nvidia’s B200 processors leverage this technology, with the latter being larger in size compared to the former.

The forthcoming CoWoS_L, anticipated for production readiness by 2026, will further enhance capabilities by accommodating interposers roughly 5.5 times the size of a standard reticle (although slightly less impressive than the initially announced 6x reticle size). This expanded space allocation will provide up to 4719 mm2 for logic circuits, accommodating up to 12 HBM memory stacks, and incorporating additional chiplets. Such System-in-Package (SiP) designs will necessitate larger substrates, projected to be 100×100 mm according to TSMC’s presentation. Consequently, processors utilizing this technology will be unable to integrate OAM modules.

Largest Chip

Looking ahead, TSMC is pushing the boundaries even further with its CoWoS technology slated for release in 2027. This iteration will facilitate interposers that are eight times larger than the standard reticle size, providing chiplets with a generous 6,864 square mm of space. One envisioned design involves four stacked Systems-on-Integrated Chips (SoICs) paired with 12 HBM4 memory stacks and additional I/O dies. However, such a colossal configuration will undoubtedly demand an immense amount of power—potentially reaching thousands of watts—and will necessitate highly sophisticated cooling technology. TSMC anticipates that these advanced solutions will require a substrate size of 120x120mm.

Consider the implications for autonomous vehicles: with chips of this size, vehicles could process sensor data in real-time, enabling safer navigation through complex urban environments.

Looking ahead to 2027, the vision of chips with an astonishing 6,864 square mm of real estate opens up possibilities for immersive virtual reality experiences that blur the lines between the digital and physical worlds.

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Power and Cooling Challenges:

While the prospect of such immense processing power is exhilarating, it also brings forth formidable challenges, particularly in terms of power consumption and thermal management. Imagine a data center powered by TSMC massive chips, where advanced cooling technologies are employed to dissipate the heat generated by kilowatts of processing power.

The result? Enhanced energy efficiency and reliability, paving the way for more sustainable and scalable computing infrastructure.

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Implications for the Future:

The implications of TSMC ambitious plans extend far beyond the realm of traditional computing.

Consider the impact on personalized medicine: with access to unprecedented computational power, researchers could analyze genomic data in real-time, leading to more targeted treatments for individual patients.

Furthermore, the advent of massive chips promises to unlock new frontiers of innovation in fields such as artificial intelligence and robotics, transforming the way we interact with technology and the world around us.

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TSMC’s pursuit of massive chips represents a paradigm shift in semiconductor design and manufacturing, with profound implications for the future of computing.

As we embark on this journey towards ever-greater computational prowess, one thing is certain: the possibilities are limitless.

From revolutionizing healthcare to powering the next generation of autonomous systems, TSMC’s ambitious plans are poised to shape the future of technology and drive human progress forward.

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