Backside power Deiivery

What is Backside Power Delivery: Intel’s Secret weapon for Foundry Leadership

Intel's pioneering "Backside Power Delivery" technology emerges as a potent weapon in the race for foundry dominance.
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In the realm of semiconductor technology, where every nanometer counts, innovations continually push the boundaries of efficiency and performance. One such innovation making waves in the industry is backside power delivery.

It refers to a method of supplying electrical power to components on the underside or backside of a semiconductor chip or integrated circuit (IC) rather than solely relying on the traditional method of routing power through the top layers of the chip. This approach involves embedding power delivery structures within the semiconductor substrate itself, allowing for more efficient distribution of power to components.

The leading foundries have ambitious plans to integrate backside power delivery starting from the 2nm node, heralding a new era of chip design characterized by swifter and more efficient switching, alleviated routing congestion, and diminished noise across multiple metal layers.

By utilizing wider and less resistive lines on the backside to deliver power, as opposed to less efficient frontside methods, power losses can be slashed by up to 30% thanks to reduced voltage drop.

In cutting-edge processors designed for advanced nodes, power lines often traverse numerous layers of interconnect, sometimes exceeding 15 layers.

Adopting backside power delivery not only conserves precious routing resources on the frontside, particularly on the initial and most costly metal layer but also mitigates various types of interactions that have significantly compounded design complexity, often stemming from unpredictable, workload-dependent physical effects.

In this article, we delve into the intricacies of backside power delivery, contrasting it with the traditional frontside approach, and exploring the challenges and solutions it presents.

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An analogy

Imagine you’re in a bustling city with narrow streets, and you need to deliver electricity to buildings located in different areas. Traditionally, you might lay power lines above ground, along the streets, which can get crowded and chaotic with all the other traffic like cars and pedestrians. This congestion can slow down the delivery of electricity and sometimes cause interference or disruptions.

Now, let’s consider backside power delivery like installing an underground network of power lines directly beneath the buildings. Instead of dealing with the crowded streets, you’re able to deliver electricity efficiently and directly to each building’s backside, avoiding the congestion and noise on the surface.

In this analogy, the crowded streets represent the top layers of a semiconductor chip, where traditional power routing can become congested and noisy. Backside power delivery, like the underground network, allows for a more efficient and direct distribution of power to the components on the underside of the chip, leading to faster operation, reduced congestion, and lower interference.

“Transistors are built first, as before, with the interconnect layers added next,” said Ben Sell, vice president of Technology Development at Intel. “Now the fun part: flip over the wafer and polish everything off to expose the bottom layer to which the wires […] for power will be connected. We call it silicon technology, but the amount of silicon that’s left on these wafers is really tiny.”

Frontside vs. Backside Power Delivery:

Frontside power delivery, the conventional method, involves routing power lines through the top layers of a semiconductor chip. While effective, this approach has limitations, including routing congestion, signal interference, and increased resistance, especially in densely packed designs.

Backside power Deiivery

Source: Intel

Backside power delivery, on the other hand, revolutionizes the game by distributing power through the substrate beneath the chip. This technique offers several advantages over frontside delivery, including faster switching speeds, reduced routing congestion, and lower noise across multiple metal layers. By bypassing the congested top layers, it optimizes power distribution, enhancing overall chip performance and energy efficiency.

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Benefits of Backside Power Delivery method

The concept of the backside power rail involves moving power lines to the back of the wafer, separate from the I/O wiring. This method addresses issues like increased resistance in the back-end-of-line (BEOL), leading to better transistor performance and lower power consumption. It also eliminates any potential interference between data and power wires and boosts the density of logic transistors.

Read More: Why Does Intel Plan to Manufacture Chips for Other Foundries As Per CEO – techovedas

Intel backside power delivery result

Source: Intel

Intel’s pioneering “Backside Power Delivery” technology emerges as a potent weapon in the race for foundry dominance.Intel’s pioneering “Backside Power Delivery” technology emerges as a potent weapon in the race for foundry dominance. However, currently, Intel views it as a significant breakthrough, comparable to past innovations like strained silicon at 90nm in 2003, Hafnium-based high-K metal gate at 45nm in 2007, and FinFET at 22nm in 2012.

According to Intel, implementing backside PDN in a test chip on an internal process node resulted in a clock speed increase of over 6%, a 30% reduction in voltage droop, and cell utilization exceeding 90% in large areas of its E-core die. Despite its benefits, building a backside power delivery network poses challenges due to various reasons.

backside Delivery Performance

Source: Intel

Challenges and Solutions:

Implementing backside power delivery presents unique challenges, but innovative solutions are paving the way for its adoption at advanced nodes:

Substrate Complexity: The substrate’s intricate structure poses challenges in designing efficient backside power delivery systems. Solutions include optimizing substrate materials and incorporating specialized power delivery structures, such as through-silicon vias (TSVs) and microvias, to streamline power distribution.

Thermal Management: Efficient heat dissipation is crucial for maintaining chip reliability and performance It can exacerbate thermal challenges due to increased power density. Advanced thermal management techniques, such as thermally conductive substrates and integrated cooling technologies, mitigate thermal hotspots and ensure optimal chip operation.

Manufacturing Complexity: Integrating backside power delivery into the chip fabrication process adds complexity to manufacturing workflows. Collaborative efforts between semiconductor manufacturers and foundries are essential to develop standardized processes and ensure seamless integration of backside power delivery into chip designs.

Signal Integrity: It must coexist harmoniously with signal paths to maintain signal integrity and minimize electromagnetic interference (EMI). Careful design considerations, including signal routing optimization and shielding techniques, address potential EMI issues and preserve signal quality.

Read More: Semiconductor Giants Seek More than Double the Chips Act Fund: Gina Raimondo – techovedas


In the second half of 2023 and the first half of 2024, Intel will introduce its PowerVia backside power delivery network with its upcoming 20A and 18A nodes, respectively. The Arrow Lake CPU, Intel’s first client processor on the 20A process, is expected to debut around mid-2024 or sooner.

These manufacturing technologies, 18A and 20A, are not only aimed at Intel’s own products but also cater to customers of Intel Foundry Services (IFS). Therefore, the introduction of PowerVia promises benefits for both Intel and its IFS clients. Whether PowerVia will prove to be a significant advantage remains to be seen, but it’s worth noting that Intel is leading the way in implementing backside power delivery, with TSMC expected to offer a similar technology much later, around late 2026 to early 2027.

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