3 Reasons Why TSMC Won't Adopt High-NA EUV Lithography Until 2032

Introduction:

In the ever-evolving landscape of semiconductor manufacturing, the adoption of cutting-edge technologies is crucial for staying competitive. Intel has recently taken a bold step by acquiring ASML’s extreme ultraviolet (EUV) lithography tool with a 0.55 numerical aperture (High-NA), signaling its commitment to advanced process technologies. However, TSMC, one of Intel main competitors, appears to be in no hurry to follow suit.

“In contrast to Intel’s use of High-NA EUV soon after its shift to GAA (planned for [20A] insertion), we expect TSMC’sHigh-NA EUV insertion in the post N1.4 era (the inflection likely at N1, scheduled for post-2030 launch),”

~Szeho Ng, an analyst with China Renaissance.

This blog post explores the reasons behind TSMC’s cautious approach, with analysts suggesting that High-NA EUV may not be on TSMC’s roadmap until 2032 or beyond.

1. Focus on Cost Competitiveness: TSMC Vs Intel

TSMC, known for targeting the volume market with cost-competitive technologies, could initially find the utilization of High-NA EUV machines more expensive than employing Low-NA EUV double patterning, as suggested by analysts at SemiAnalysis and China Renaissance.

Intel’s ambitious technology development plan involves integrating RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery network (BSPDN) in the 20A (20 angstroms, 2nm-class) process. Subsequently, these technologies will be further enhanced in the 18A process.

The company aims to leverage High-NA EUV tools in a subsequent post-18A node to deliver optimal power, performance, area characteristics, and minimize cycle time.

“Low-NA EUV multiple patterning, despite lower throughput on more exposure passes, may still cost less than high-NA EUV in the initial GAA foray; the higher source power of high-NA EUV to drive finer CD (critical dimension) speeds up wear on projection optics and photomasks, outweighing higher throughput benefits, This ties with TSMC’s practice to target the volume market with the most cost-competitive technologies.”

~ China Renaissance

Image Credits: ASML

2. Production Complexities and Lower Transistor Density Concerns:

Let’s break down the key Production challenges associated with High-NA EUV lithography tools:

Reduced Exposure Field:

High-NA EUV lithography tools have a 2x reduced exposure field compared to their Low-NA counterparts. The exposure field refers to the area of the semiconductor wafer that can be effectively exposed by the lithography tool in a single exposure shot.

A reduced exposure field means that the lithography tool covers a smaller portion of the wafer surface with each exposure. This necessitates additional exposures to cover the entire wafer.

Higher Source Power for Finer Critical Dimensions (CD):

Higher source power in the lithography process is necessary to achieve finer critical dimensions (CD). CD represents the smallest features accurately reproduced on the semiconductor wafer. In EUV lithography, the intensity of the extreme ultraviolet light used to create patterns on the wafer is termed source power.

The higher source power is necessary for achieving the precision required for smaller CD, . This enables the fabrication of more advanced and densely packed semiconductor components.

Increased Wear on Projection Optics and Photomasks:

The combination of a reduced exposure field and the need for higher source power comes with a trade-off.

The increased intensity of the EUV light, especially in High-NA lithography, can lead to greater wear and degradation of the projection optics and photomasks used in the lithography process.

Projection Optics: These are the lenses and mirrors that focus and project the EUV light onto the wafer. The higher intensity of the light can cause more rapid wear on these components, affecting their performance over time.
Photomasks: Photomasks are critical in defining the patterns that are transferred onto the semiconductor wafer. The increased source power may result in more frequent replacement or maintenance of photomasks due to wear and damage caused during the lithography process.

TSMC, known for its meticulous approach to production processes, may be hesitant to embrace High-NA EUV due to concerns about production complexities and potential compromises in transistor density.

3. TSMC Successful Track Record with Existing Technologies in Contrast to Intel:

EUV lithography tools with Low-NA (numerical aperture) lenses, featuring a 0.33 numerical aperture, currently offer a feasible critical dimension ranging from 13 to 16 nm for mass production.

This capability allows for the creation of a minimum metal pitch of 26 nm and an estimated tip-to-tip interconnect space pitch of 25 to 30 nm using single exposure patterning.

These specifications are suitable for a 3nm-class process technology, characterized by metal pitches between 21 and 24 nm.

5 Major Players in Foundry Market Share — TSMC leads the foundry market share

As semiconductor technology progresses to 2nm and beyond, metal pitches are projected to shrink to 18–21 nm, according to imec. Coping with this reduction requires advanced techniques like EUV double patterning, pattern shaping equipment, or High-NA single patterning.

Analysts Szeho Ng, predict that TSMC might consider High-NA EUV insertion in the post N1.4 era, likely after 2030. This strategic timing aligns with TSMC’s historical approach of carefully assessing market dynamics and competitors’ moves before making significant technological shifts.

Waiting until 2032 or beyond could allow TSMC to observe the successes and challenges faced by Intel, providing valuable insights for a smoother adoption process.

Conclusion:

Intel is aggressively advancing its process technology with High-NA EUV lithography, while TSMC takes a measured approach to uphold cost competitiveness and manage production complexities. TSMC’s decision to postpone High-NA EUV adoption until 2032 is a strategic move, not a reluctance to embrace innovation, setting the stage for dynamic competition in the semiconductor industry.

Reference: Semianalysis and China resistance

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