4 Ways TSMC is Scaling Below 2nm and Beyond

Introduction

The semiconductor industry stands at the cusp of another monumental transition – the long-awaited shift to 2nm process technology. For decades, chipmakers have adhered to Moore’s Law, doubling transistor density every two years. However, as geometries shrink below 5nm, doubt has crept in. Have we pushed silicon fabrication to its physical limits? Can innovation propel us forward? To find out, we articulated the highlights of a conversation between Mark Papermaster, CTO & EVP of AMD and Dr. YJ Mii, EVP of Taiwan Semiconductor Manufacturing Corporation (TSMC), on the challenges and breakthroughs driving progress toward 2nm and beyond.

The TSMC Road to 2nm: No Shortage of Obstacles

TSMC has spearheaded semiconductor manufacturing for over 30 years, with Dr. Mii himself joining the company at the advent of 0.5-micron fabrication. Since then, transistor density has exploded over 4000X to prepare the first 2nm production lines. However, complexity increases exponentially with each new node. Each generation now requires up to 7 years from initial research to volume production compared to 2-3 years previously.

So where does this complexity originate? Firstly, node transitions mandate innovations across the entire manufacturing stack – new materials, process technologies, and metrology. Learning to integrate and scale these in tandem while maintaining yields is itself a grand challenge. Secondly, performance no longer stems predominantly from density scaling. Equal or greater improvements come from boosting speed and reducing power. This depends on optimization across device physics, interconnect systems, chip architectures, and application-specific accelerators. Managing all these vectors simultaneously to deliver tangible gains for customers represents the ultimate balancing act.

1. Shifting from FinFETs to GAA transistors

Transitioning to 2nm itself brings the long-expected shift from FinFETs to gate-all-around nanosheet transistors. This new generation of transistors have Gate All-Around the transistor channel. So, it has better control of the transistor performance and short channel effects.

This reengineered structure promises phenomenal efficiency gains. However, rebuilding process flows for GAAfets brings daunting trials. Regardless, TSMC seems firmly on track for 2nm production by 2025. So what new methods are powering this progress?

2. The Co-Optimization Imperative

Dr. Mii tells that realizing the potential of new technologies depends more and more on design and technology co-optimization (DTCO). Each new node brings more complex design rules and device models – too much for design teams to fully leverage alone. Instead, they must align closely with foundries and EDA partners. TSMC now engages with customers from the earliest research stages and co-develops process flavours tailored for each application space.

We see the fruits of co-optimization clearly in AMD’s partnership with TSMC. Their engineering teams operate as extensions of each other – exploring innovations across logic and packaging technologies. This collaboration has already produced major wins like the MI300 GPU on TSMC’s 3D Fabric packaging. As we move to 2nm, DTCO will grow even more decisive.

3. TSMC Still sees 2D scaling has something left

While challenges abound, TSMC sees abundant room for advancing computing power further. Firstly, 2D scaling still promises headroom by optimizing for performance and power efficiency.

For decades, chipmakers have been able to reliably reduce the planar geometries of transistors and interconnects to pack more computing power per unit area, which is known as 2D scaling. This is a major driver behind the exponential increase of transistor density observed in Moore’s Law.

However, as fabrication processes move below 5nm and beyond, 2D scaling faces significant challenges from both technological and economic perspectives.

Nonetheless, industry leaders like TSMC believe there is still headroom left in 2D scaling by optimizing parameters like channel materials, architecture, strain engineering, etc. to deliver better performance and power efficiency, if not strictly higher density.

4. 3D integration for going beyond 2nm

Novel 3D integration techniques can multiply density. TSMC is researching a 3D transistor structure called CFET (complementary FET), which stacks NMOS and PMOS transistors vertically. This CFET configuration itself can bring additional density benefit as well as power efficiency because you moving to smaller dimensions.

TSMC already has its eyes on stacked nanosheet transistors, advanced 3D packaging, and high-bandwidth memory integration with photonics. They also see the fledgling AI compute industry driving demand for extreme performance.

However, to realize these innovations, semiconductor manufacturers cannot work in isolation. Tool vendors must co-optimize etch and deposition processes. Software partners need to evolve modelling and design automation. Most critically, chipmakers must articulate their application needs years ahead to guide development. Dr. Mii believes the strength of TSMC’s foundry model stems from accommodating this diversity of clients and co-innovating with them.

Conclusion

TSMC Pushing past 2nm to advance computing could certainly rank among humanity’s most complex engineering endeavours. However, TSMC stands well-poised to overcome these hurdles. Its unmatched experience, rigorous execution, and early investments in co-design and next-generation technologies set the stage for transcending perceived limitations. If current projections hold true, Moore’s Law will perpetuate through holistic innovation across the semiconductor stack – ushering in a new era of high-performance computing.